A Preliminary Study on the Design of Hierarchical Memory Management for Heterogeneous Architectures

• Item type: SIG Technical Reports(1)
• 公開日: 2012-07-25
• タイトル: A Preliminary Study on the Design of Hierarchical Memory Management for Heterogeneous Architectures
• タイトル / 言語: en
• タイトル: A Preliminary Study on the Design of Hierarchical Memory Management for Heterogeneous Architectures
• 言語: eng
• キーワード / 主題Scheme: Other
• キーワード / 主題: メモリ管理
• 資源タイプ / 資源タイプ識別子: http://purl.org/coar/resource_type/c_18gh
• 資源タイプ: technical report
• 著者所属: RIKEN Advanced Institute for Computational Science
• 著者所属: RIKEN Advanced Institute for Computational Science
• 著者所属: RIKEN Advanced Institute for Computational Science
• 著者所属: Graduate School of Information Science and Technology The University of Tokyo／RIKEN Advanced Institute for Computational Science
• 著者所属(英): en
• 著者所属(英): RIKEN Advanced Institute for Computational Science
• 著者所属(英): en
• 著者所属(英): RIKEN Advanced Institute for Computational Science
• 著者所属(英): en
• 著者所属(英): RIKEN Advanced Institute for Computational Science
• 著者所属(英): en
• 著者所属(英): Graduate School of Information Science and Technology The University of Tokyo／RIKEN Advanced Institute for Computational Science
• 著者名: Balazs, Gerofi; Akio, Shimada; Atsushi, Hori; Yutaka, Ishikawa
• 著者名(英): Balazs, Gerofi; Akio, Shimada; Atsushi, Hori; Yutaka, Ishikawa
• 論文抄録 / 内容記述タイプ: Other
• 論文抄録 / 内容記述: Heterogeneous architectures, where a multicore processor, which is optimized for fast single-thread performance, is accompanied with a large number of simpler, but more power-efficient cores optimized for parallel workloads, are receiving a lot attention recently. Currently, these co-processors, such as Intel's Many Integrated Core (MIC) software development platform, come with a limited on-board RAM, which requires partitioning computational problems manually into pieces that can fit into the device's memory, and at the same time, efficiently overlapping computation and communication. In this paper we explore the design considerations for operating system (OS) assisted hierarchical memory management, relying on the capabilities of the Intel MIC's memory management unit (MMU). We are aiming at transparent data movement between the device and the host memory, as well as tight integration with other OS services, such as file and network I/O.
• 論文抄録(英) / 内容記述タイプ: Other
• 論文抄録(英) / 内容記述: Heterogeneous architectures, where a multicore processor, which is optimized for fast single-thread performance, is accompanied with a large number of simpler, but more power-efficient cores optimized for parallel workloads, are receiving a lot attention recently. Currently, these co-processors, such as Intel's Many Integrated Core (MIC) software development platform, come with a limited on-board RAM, which requires partitioning computational problems manually into pieces that can fit into the device's memory, and at the same time, efficiently overlapping computation and communication. In this paper we explore the design considerations for operating system (OS) assisted hierarchical memory management, relying on the capabilities of the Intel MIC's memory management unit (MMU). We are aiming at transparent data movement between the device and the host memory, as well as tight integration with other OS services, such as file and network I/O.
• 書誌レコードID / 収録物識別子タイプ: NCID
• 書誌レコードID / 収録物識別子: AN10444176
• 書誌情報: 研究報告システムソフトウェアとオペレーティング・システム（OS）; 巻 2012-OS-122, 号 17, p. 1-5, 発行日 2012-07-25
• Notice: SIG Technical Reports are nonrefereed and hence may later appear in any journals, conferences, symposia, etc.
• 出版者 / 言語: ja
• 出版者: 情報処理学会