Deep DVS in FU Array by Covering Process Variations with Data-Path Auto-fix

• Item type: SIG Technical Reports(1)
• 公開日: 2012-04-30
• タイトル: Deep DVS in FU Array by Covering Process Variations with Data-Path Auto-fix
• タイトル / 言語: en
• タイトル: Deep DVS in FU Array by Covering Process Variations with Data-Path Auto-fix
• 言語: eng
• キーワード / 主題Scheme: Other
• キーワード / 主題: 低消費電力
• 資源タイプ / 資源タイプ識別子: http://purl.org/coar/resource_type/c_18gh
• 資源タイプ: technical report
• 著者所属: Nara Institute of Science and Technology
• 著者所属: Nara Institute of Science and Technology
• 著者所属(英): en
• 著者所属(英): Nara Institute of Science and Technology
• 著者所属(英): en
• 著者所属(英): Nara Institute of Science and Technology
• 著者名: Jun, Yao; Yasuhiko, Nakashima
• 著者名(英): Jun, Yao; Yasuhiko, Nakashima
• 論文抄録 / 内容記述タイプ: Other
• 論文抄録 / 内容記述: Process variability in advanced semiconductor technologies has become a major constraint for improving the working frequency, especially under voltage scaling. In this research, based on a full understanding of unit utilization in an FU array accelerator, we propose a method to auto-fix the execution hardware data-path so as to include units with tolerable process variations. This method can help apply a deep DVS to achieve a nearly optimal energy reduction which is usually not possible due to the worst case process variation. A preliminary simulation result indicates that even after an aggressive power-gating, a 21.9% energy reduction without any performance impact can still be achieved by avoiding adverse and using beneficial process variations.
• 論文抄録(英) / 内容記述タイプ: Other
• 論文抄録(英) / 内容記述: Process variability in advanced semiconductor technologies has become a major constraint for improving the working frequency, especially under voltage scaling. In this research, based on a full understanding of unit utilization in an FU array accelerator, we propose a method to auto-fix the execution hardware data-path so as to include units with tolerable process variations. This method can help apply a deep DVS to achieve a nearly optimal energy reduction which is usually not possible due to the worst case process variation. A preliminary simulation result indicates that even after an aggressive power-gating, a 21.9% energy reduction without any performance impact can still be achieved by avoiding adverse and using beneficial process variations.
• 書誌レコードID / 収録物識別子タイプ: NCID
• 書誌レコードID / 収録物識別子: AN10444176
• 書誌情報: 研究報告システムソフトウェアとオペレーティング・システム（OS）; 巻 2012-OS-121, 号 18, p. 1-9, 発行日 2012-04-30
• Notice: SIG Technical Reports are nonrefereed and hence may later appear in any journals, conferences, symposia, etc.
• 出版者 / 言語: ja
• 出版者: 情報処理学会