Item type |
Trans(1) |
公開日 |
2012-02-21 |
タイトル |
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タイトル |
A Robust Algorithm for Pessimistic Analysis of Logic Masking Effects in Combinational Circuits |
タイトル |
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言語 |
en |
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タイトル |
A Robust Algorithm for Pessimistic Analysis of Logic Masking Effects in Combinational Circuits |
言語 |
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言語 |
eng |
キーワード |
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主題Scheme |
Other |
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主題 |
Logic-Level Reliability Analysis(Outstanding Paper Award、優秀論文賞受賞) |
資源タイプ |
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資源タイプ識別子 |
http://purl.org/coar/resource_type/c_6501 |
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資源タイプ |
journal article |
著者所属 |
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Department of Computer Science and Communication Engineering, Kyushu University |
著者所属 |
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Department of Computer Science and Communication Engineering, Kyushu University |
著者所属(英) |
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en |
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Department of Computer Science and Communication Engineering, Kyushu University |
著者所属(英) |
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en |
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Department of Computer Science and Communication Engineering, Kyushu University |
著者名 |
Taiga, Takata
Yusuke, Matsunaga
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著者名(英) |
Taiga, Takata
Yusuke, Matsunaga
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論文抄録 |
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内容記述タイプ |
Other |
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内容記述 |
Analyzing logic masking effects is an important key to evaluate soft error tolerance of circuits. The computing complexity of analyzing logic masking effects exactly is proportional to the square of circuit size, which is unacceptable to achieve a scalable analyzer. This paper shows a robust algorithm to analyze logic masking effects pessimistically with multiple CODCs (Compatible combinations of Observability Don't Cares). It is guaranteed that an upper bound of the susceptibility of each gate is estimated using the proposed algorithm. The computing complexity of the proposed algorithm is proportional to circuit size. Experimental results show that the proposed algorithm runs about 91 times faster than an algorithm which analyzes logic masking effects exactly with fault simulation. The proposed algorithm estimates average susceptibility 11.5% larger than that of the exact algorithm for circuits in ITC'99 benchmark set. The state-of-the-art heuristic AnSER estimates average susceptibility with 96% underestimation for circuits protected with partial TMR (Triple Modular Redundancy) on average, which can be fatal error for soft error tolerance evaluation. On the other hand, the proposed algorithm estimates average susceptibility with 37.9% overestimation for such circuits on average. The proposed algorithm is useful to estimate an upper bound of the susceptibility of each gate quickly. |
論文抄録(英) |
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内容記述タイプ |
Other |
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内容記述 |
Analyzing logic masking effects is an important key to evaluate soft error tolerance of circuits. The computing complexity of analyzing logic masking effects exactly is proportional to the square of circuit size, which is unacceptable to achieve a scalable analyzer. This paper shows a robust algorithm to analyze logic masking effects pessimistically with multiple CODCs (Compatible combinations of Observability Don't Cares). It is guaranteed that an upper bound of the susceptibility of each gate is estimated using the proposed algorithm. The computing complexity of the proposed algorithm is proportional to circuit size. Experimental results show that the proposed algorithm runs about 91 times faster than an algorithm which analyzes logic masking effects exactly with fault simulation. The proposed algorithm estimates average susceptibility 11.5% larger than that of the exact algorithm for circuits in ITC'99 benchmark set. The state-of-the-art heuristic AnSER estimates average susceptibility with 96% underestimation for circuits protected with partial TMR (Triple Modular Redundancy) on average, which can be fatal error for soft error tolerance evaluation. On the other hand, the proposed algorithm estimates average susceptibility with 37.9% overestimation for such circuits on average. The proposed algorithm is useful to estimate an upper bound of the susceptibility of each gate quickly. |
書誌レコードID |
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収録物識別子タイプ |
NCID |
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収録物識別子 |
AA12394951 |
書誌情報 |
IPSJ Transactions on System LSI Design Methodology(TSLDM)
巻 5,
p. 55-62,
発行日 2012-02-21
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ISSN |
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収録物識別子タイプ |
ISSN |
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収録物識別子 |
1882-6687 |
出版者 |
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言語 |
ja |
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出版者 |
情報処理学会 |