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Achieving Effective Fault Tolerance in FU array by Adding AVF Awareness
https://ipsj.ixsq.nii.ac.jp/records/81325
https://ipsj.ixsq.nii.ac.jp/records/81325158e6a79-5105-407d-84af-6f06e65c86af
名前 / ファイル | ライセンス | アクション |
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Copyright (c) 2012 by the Information Processing Society of Japan
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オープンアクセス |
Item type | SIG Technical Reports(1) | |||||||
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公開日 | 2012-03-20 | |||||||
タイトル | ||||||||
タイトル | Achieving Effective Fault Tolerance in FU array by Adding AVF Awareness | |||||||
タイトル | ||||||||
言語 | en | |||||||
タイトル | Achieving Effective Fault Tolerance in FU array by Adding AVF Awareness | |||||||
言語 | ||||||||
言語 | eng | |||||||
キーワード | ||||||||
主題Scheme | Other | |||||||
主題 | 信頼性 | |||||||
資源タイプ | ||||||||
資源タイプ識別子 | http://purl.org/coar/resource_type/c_18gh | |||||||
資源タイプ | technical report | |||||||
著者所属 | ||||||||
Nara Institute of Science & Technology | ||||||||
著者所属 | ||||||||
Nara Institute of Science & Technology | ||||||||
著者所属 | ||||||||
Nara Institute of Science & Technology | ||||||||
著者所属(英) | ||||||||
en | ||||||||
Nara Institute of Science & Technology | ||||||||
著者所属(英) | ||||||||
en | ||||||||
Nara Institute of Science & Technology | ||||||||
著者所属(英) | ||||||||
en | ||||||||
Nara Institute of Science & Technology | ||||||||
著者名 |
Tanvir, Ahmed
× Tanvir, Ahmed
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著者名(英) |
Tanvir, Ahmed
× Tanvir, Ahmed
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論文抄録 | ||||||||
内容記述タイプ | Other | |||||||
内容記述 | Fault-tolerance now plays an important role to cover the increasing soft/hard error rates in electronic devices along the advances of process technologies. Error detection with negligible performance impedance and low hardware overhead is accordingly a main concern to keep efficient high dependability. In this paper, a fault-tolerable FU array is proposed with the awareness of architectural vulnerable factor (AVFs). Specifically, we designed a method to help fast locate the erroneous execution in FU array by effectively checking the most vulnerable branches of the data path. It can be further applied to detect multi-site faults or to reduce less important redundancy. | |||||||
論文抄録(英) | ||||||||
内容記述タイプ | Other | |||||||
内容記述 | Fault-tolerance now plays an important role to cover the increasing soft/hard error rates in electronic devices along the advances of process technologies. Error detection with negligible performance impedance and low hardware overhead is accordingly a main concern to keep efficient high dependability. In this paper, a fault-tolerable FU array is proposed with the awareness of architectural vulnerable factor (AVFs). Specifically, we designed a method to help fast locate the erroneous execution in FU array by effectively checking the most vulnerable branches of the data path. It can be further applied to detect multi-site faults or to reduce less important redundancy. | |||||||
書誌レコードID | ||||||||
収録物識別子タイプ | NCID | |||||||
収録物識別子 | AN10096105 | |||||||
書誌情報 |
研究報告計算機アーキテクチャ(ARC) 巻 2012-ARC-199, 号 5, p. 1-4, 発行日 2012-03-20 |
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Notice | ||||||||
SIG Technical Reports are nonrefereed and hence may later appear in any journals, conferences, symposia, etc. | ||||||||
出版者 | ||||||||
言語 | ja | |||||||
出版者 | 情報処理学会 |