Design and Implementation Fine-grained Power Gating on Microprocessor Functional Units

• Item type: Trans(1)
• 公開日: 2011-08-10
• タイトル: Design and Implementation Fine-grained Power Gating on Microprocessor Functional Units
• タイトル / 言語: en
• タイトル: Design and Implementation Fine-grained Power Gating on Microprocessor Functional Units
• 言語: eng
• キーワード / 主題Scheme: Other
• キーワード / 主題: Architectural Low-Power Design
• 資源タイプ / 資源タイプ識別子: http://purl.org/coar/resource_type/c_6501
• 資源タイプ: journal article
• 著者所属: Keio University / Graduate School of Information Systems, University of Electro-Communications
• 著者所属: Keio University
• 著者所属: Shibaura Institute of Technology
• 著者所属: Tokyo University of Agriculture and Technology
• 著者所属: Graduate School of Information Systems, University of Electro-Communications
• 著者所属: The University of Tokyo
• 著者所属: Keio University
• 著者所属(英): en
• 著者所属(英): Keio University / Graduate School of Information Systems, University of Electro-Communications
• 著者所属(英): en
• 著者所属(英): Keio University
• 著者所属(英): en
• 著者所属(英): Shibaura Institute of Technology
• 著者所属(英): en
• 著者所属(英): Tokyo University of Agriculture and Technology
• 著者所属(英): en
• 著者所属(英): Graduate School of Information Systems, University of Electro-Communications
• 著者所属(英): en
• 著者所属(英): The University of Tokyo
• 著者所属(英): en
• 著者所属(英): Keio University
• 著者名: Zhao, Lei; Daisuke, Ikebuchi; Kimiyoshi, Usami; Mitaro, Namiki; Masaaki, Kondo; Hiroshi, Nakamura; Hideharu, Amano
• 著者名(英): Zhao, Lei; Daisuke, Ikebuchi; Kimiyoshi, Usami; Mitaro, Namiki; Masaaki, Kondo; Hiroshi, Nakamura; Hideharu, Amano
• 論文抄録 / 内容記述タイプ: Other
• 論文抄録 / 内容記述: In this paper, we present a prototype MIPS R3000 processor, which integrates the fine-grained power gating technique into its functional units. To reduce the leakage power consumption, functional units, such as multiplier and divider can be power-gated individually according to the workload of the execution program. The prototype chip -- Geyser-1 has been implemented with Fujitsu's 65nm CMOS technology; and to facilitate the design process with fine-grained power gating, a fully automated design flow has also been proposed. Comprehensive real-chip evaluations have been performed to verify the leakage reduction efficiency. According the evaluation results with benchmark programs, the fine-grained power gating can reduce the power of the processor by 5% at 25℃ and 23% at 80℃.
• 論文抄録(英) / 内容記述タイプ: Other
• 論文抄録(英) / 内容記述: In this paper, we present a prototype MIPS R3000 processor, which integrates the fine-grained power gating technique into its functional units. To reduce the leakage power consumption, functional units, such as multiplier and divider can be power-gated individually according to the workload of the execution program. The prototype chip -- Geyser-1 has been implemented with Fujitsu's 65nm CMOS technology; and to facilitate the design process with fine-grained power gating, a fully automated design flow has also been proposed. Comprehensive real-chip evaluations have been performed to verify the leakage reduction efficiency. According the evaluation results with benchmark programs, the fine-grained power gating can reduce the power of the processor by 5% at 25℃ and 23% at 80℃.
• 書誌レコードID / 収録物識別子タイプ: NCID
• 書誌レコードID / 収録物識別子: AA12394951
• 書誌情報: IPSJ Transactions on System LSI Design Methodology（TSLDM）; 巻 4, p. 182-192, 発行日 2011-08-10
• ISSN / 収録物識別子タイプ: ISSN
• ISSN / 収録物識別子: 1882-6687
• 出版者 / 言語: ja
• 出版者: 情報処理学会