Partial Product Generation Utilizing the Sum of Operands for Reduced Area Parallel Multipliers

• Item type: Trans(1)
• 公開日: 2011-08-10
• タイトル: Partial Product Generation Utilizing the Sum of Operands for Reduced Area Parallel Multipliers
• タイトル / 言語: en
• タイトル: Partial Product Generation Utilizing the Sum of Operands for Reduced Area Parallel Multipliers
• 言語: eng
• キーワード / 主題Scheme: Other
• キーワード / 主題: Arithmetic Design Optimization
• 資源タイプ / 資源タイプ識別子: http://purl.org/coar/resource_type/c_6501
• 資源タイプ: journal article
• 著者所属: The Center for Embedded Computing Systems, Graduate School of Information Science, Nagoya University
• 著者所属: Department of Communications and Computer Engineering, Graduate School of Informatics, Kyoto University
• 著者所属(英): en
• 著者所属(英): The Center for Embedded Computing Systems, Graduate School of Information Science, Nagoya University
• 著者所属(英): en
• 著者所属(英): Department of Communications and Computer Engineering, Graduate School of Informatics, Kyoto University
• 著者名: Hirotaka, Kawashima; Naofumi, Takagi
• 著者名(英): Hirotaka, Kawashima; Naofumi, Takagi
• 論文抄録 / 内容記述タイプ: Other
• 論文抄録 / 内容記述: We propose a novel method to generate partial products for reduced area parallel multipliers. Our method reduces the total number of partial product bits of parallel multiplication by about half. We call partial products generated by our method Compound Partial Products (CPPs). Each CPP has four candidate values: zero, a part of the multiplicand, a part of the multiplier and a part of the sum of the operands. Our method selects one from the four candidates according to a pair of a multiplicand bit and a multiplier bit. Multipliers employing the CPPs are approximately 30% smaller than array multipliers without radix-4 Booth's method, and approximately up to 10% smaller than array multipliers with radix-4 Booth's method. We also propose an acceleration method of the multipliers using CPPs.
• 論文抄録(英) / 内容記述タイプ: Other
• 論文抄録(英) / 内容記述: We propose a novel method to generate partial products for reduced area parallel multipliers. Our method reduces the total number of partial product bits of parallel multiplication by about half. We call partial products generated by our method Compound Partial Products (CPPs). Each CPP has four candidate values: zero, a part of the multiplicand, a part of the multiplier and a part of the sum of the operands. Our method selects one from the four candidates according to a pair of a multiplicand bit and a multiplier bit. Multipliers employing the CPPs are approximately 30% smaller than array multipliers without radix-4 Booth's method, and approximately up to 10% smaller than array multipliers with radix-4 Booth's method. We also propose an acceleration method of the multipliers using CPPs.
• 書誌レコードID / 収録物識別子タイプ: NCID
• 書誌レコードID / 収録物識別子: AA12394951
• 書誌情報: IPSJ Transactions on System LSI Design Methodology（TSLDM）; 巻 4, p. 131-139, 発行日 2011-08-10
• ISSN / 収録物識別子タイプ: ISSN
• ISSN / 収録物識別子: 1882-6687
• 出版者 / 言語: ja
• 出版者: 情報処理学会