The Implementation of a Low Cost Single-cycle On-chip Router Based on Multiple Virtual Output Queuing

• Item type: Trans(1)
• 公開日: 2011-02-28
• タイトル: The Implementation of a Low Cost Single-cycle On-chip Router Based on Multiple Virtual Output Queuing
• タイトル / 言語: en
• タイトル: The Implementation of a Low Cost Single-cycle On-chip Router Based on Multiple Virtual Output Queuing
• 言語: eng
• キーワード / 主題Scheme: Other
• キーワード / 主題: 相互結合網
• 資源タイプ / 資源タイプ識別子: http://purl.org/coar/resource_type/c_6501
• 資源タイプ: journal article
• 著者所属: Department of Computer Science, Ritsumeikan University
• 著者所属: Department of Computer Science, Ritsumeikan University
• 著者所属(英): en
• 著者所属(英): Department of Computer Science, Ritsumeikan University
• 著者所属(英): en
• 著者所属(英): Department of Computer Science, Ritsumeikan University
• 著者名: SonTruongNguyen; Shigeru, Oyanagi
• 著者名(英): Son, TruongNguyen; Shigeru, Oyanagi
• 論文抄録 / 内容記述タイプ: Other
• 論文抄録 / 内容記述: Network-on-Chip (NoC) is becoming a popular solution for communication on System-on-Chips. A router is a major component of NoC which is responsible for handling the communication. Its architecture significantly impacts on the performance of NoC. In this paper, we propose a low latency router architecture based on virtual output queuing (VOQ). The number of pipeline stages of a packet transfer can be reduced to one stage, by using VOQ buffers and speculatively performing switch allocation and switch traversal in parallel. This paper also proposes a multiple VOQ architecture for which each input port maintains multiple queues for each output channel to improve the throughput of the router. We have implemented the proposed router on FPGA and evaluated in terms of communication latency, throughput and hardware amount. The experimental results show that in a 4 × 4 two-dimensional mesh network, the proposed multiple VOQ router reduces the communication latency by 25% and cost of area by 15.6% as compared to the look-ahead speculative virtual channel router.
• 論文抄録(英) / 内容記述タイプ: Other
• 論文抄録(英) / 内容記述: Network-on-Chip (NoC) is becoming a popular solution for communication on System-on-Chips. A router is a major component of NoC which is responsible for handling the communication. Its architecture significantly impacts on the performance of NoC. In this paper, we propose a low latency router architecture based on virtual output queuing (VOQ). The number of pipeline stages of a packet transfer can be reduced to one stage, by using VOQ buffers and speculatively performing switch allocation and switch traversal in parallel. This paper also proposes a multiple VOQ architecture for which each input port maintains multiple queues for each output channel to improve the throughput of the router. We have implemented the proposed router on FPGA and evaluated in terms of communication latency, throughput and hardware amount. The experimental results show that in a 4 × 4 two-dimensional mesh network, the proposed multiple VOQ router reduces the communication latency by 25% and cost of area by 15.6% as compared to the look-ahead speculative virtual channel router.
• 書誌レコードID / 収録物識別子タイプ: NCID
• 書誌レコードID / 収録物識別子: AA11833852
• 書誌情報: 情報処理学会論文誌コンピューティングシステム（ACS）; 巻 4, 号 1, p. 43-52, 発行日 2011-02-28
• ISSN / 収録物識別子タイプ: ISSN
• ISSN / 収録物識別子: 1882-7829
• 出版者 / 言語: ja
• 出版者: 情報処理学会