Programmable Architectures and Design Methods for Two-Variable Numeric Function Generators

• Item type: Trans(1)
• 公開日: 2010-02-15
• タイトル: Programmable Architectures and Design Methods for Two-Variable Numeric Function Generators
• タイトル / 言語: en
• タイトル: Programmable Architectures and Design Methods for Two-Variable Numeric Function Generators
• 言語: eng
• キーワード / 主題Scheme: Other
• キーワード / 主題: Arithmetic Circuit Synthesis（Outstanding Paper Award、優秀論文賞受賞）
• 資源タイプ / 資源タイプ識別子: http://purl.org/coar/resource_type/c_6501
• 資源タイプ: journal article
• 著者所属: Hiroshima City University
• 著者所属: Kyushu Institute of Technology
• 著者所属: Naval Postgraduate School
• 著者所属(英): en
• 著者所属(英): Hiroshima City University
• 著者所属(英): en
• 著者所属(英): Kyushu Institute of Technology
• 著者所属(英): en
• 著者所属(英): Naval Postgraduate School
• 著者名: Shinobu, Nagayama; Tsutomu, Sasao; JonT.Butler
• 著者名(英): Shinobu, Nagayama; Tsutomu, Sasao; Jon, T.Butler
• 論文抄録 / 内容記述タイプ: Other
• 論文抄録 / 内容記述: This paper proposes programmable architectures and design methods for numeric function generators (NFGs) of two-variable functions. To realize a twovariable function in hardware, we partition a given domain of the function into segments, and approximate the function by a polynomial in each segment. This paper introduces two planar segmentation algorithms that efficiently partition a domain of a two-variable function. This paper also introduces a design method for symmetric two-variable functions (i.e. f(X, Y) = f(Y,X)). This method can reduce the memory size needed for symmetric functions by nearly half with small speed penalty. The proposed architectures allow a systematic design of various two-variable functions. We compare our approach with one based on a one-variable NFG. FPGA implementation results show that, for a complicated function, our NFG achieves 57% of memory size and 60% of delay time of a circuit designed based on a one-variable NFG.
• 論文抄録(英) / 内容記述タイプ: Other
• 論文抄録(英) / 内容記述: This paper proposes programmable architectures and design methods for numeric function generators (NFGs) of two-variable functions. To realize a twovariable function in hardware, we partition a given domain of the function into segments, and approximate the function by a polynomial in each segment. This paper introduces two planar segmentation algorithms that efficiently partition a domain of a two-variable function. This paper also introduces a design method for symmetric two-variable functions (i.e. f(X, Y) = f(Y,X)). This method can reduce the memory size needed for symmetric functions by nearly half with small speed penalty. The proposed architectures allow a systematic design of various two-variable functions. We compare our approach with one based on a one-variable NFG. FPGA implementation results show that, for a complicated function, our NFG achieves 57% of memory size and 60% of delay time of a circuit designed based on a one-variable NFG.
• 書誌レコードID / 収録物識別子タイプ: NCID
• 書誌レコードID / 収録物識別子: AA12394951
• 書誌情報: IPSJ Transactions on System LSI Design Methodology（TSLDM）; 巻 3, p. 118-129, 発行日 2010-02-15
• ISSN / 収録物識別子タイプ: ISSN
• ISSN / 収録物識別子: 1882-6687
• 出版者 / 言語: ja
• 出版者: 情報処理学会