Checker Generation of Assertions with Local Variables for Model Checking

• Item type: Trans(1)
• 公開日: 2009-02-17
• タイトル: Checker Generation of Assertions with Local Variables for Model Checking
• タイトル / 言語: en
• タイトル: Checker Generation of Assertions with Local Variables for Model Checking
• 言語: eng
• キーワード / 主題Scheme: Other
• キーワード / 主題: Formal Logic Verification
• 資源タイプ / 資源タイプ識別子: http://purl.org/coar/resource_type/c_6501
• 資源タイプ: journal article
• 著者所属: Osaka University, Presently with Hitachi Government and Public Corporation System Engineering Corp
• 著者所属: Osaka University
• 著者所属: Osaka University
• 著者所属(英): en
• 著者所属(英): Osaka University,Presently with Hitachi Government and Public Corporation System Engineering Corp
• 著者所属(英): en
• 著者所属(英): Osaka University
• 著者所属(英): en
• 著者所属(英): Osaka University
• 著者名: Sho, Takeuchi; Kiyoharu, Hamaguchi; Toshinobu, Kashiwabara
• 著者名(英): Sho, Takeuchi; Kiyoharu, Hamaguchi; Toshinobu, Kashiwabara
• 論文抄録 / 内容記述タイプ: Other
• 論文抄録 / 内容記述: To perform functional formal verification, model checking for assertions has attracted attentions. In SystemVerilog, assertions are allowed to include "local variables", which are used to store and refer to data values locally within assertions. For the purpose of model checking, a finite automaton called "checker" is generated. In the previous approach for checker generation by Long and Seawright, the checker introduces new state variables corresponding to a local variable. The number of the introduced state variables for each local variable, is linear to the size of a given assertion. In this paper, we show an algorithm for checker generation in order to reduce the number of the introduced state variables. In particular, our algorithm requires only one such variable for each local variable. We also show experimental results on bounded model checking for our algorithm compared with the previous work by Long and Seawright.
• 論文抄録(英) / 内容記述タイプ: Other
• 論文抄録(英) / 内容記述: To perform functional formal verification, model checking for assertions has attracted attentions. In SystemVerilog, assertions are allowed to include "local variables", which are used to store and refer to data values locally within assertions. For the purpose of model checking, a finite automaton called "checker" is generated. In the previous approach for checker generation by Long and Seawright, the checker introduces new state variables corresponding to a local variable. The number of the introduced state variables for each local variable, is linear to the size of a given assertion. In this paper, we show an algorithm for checker generation in order to reduce the number of the introduced state variables. In particular, our algorithm requires only one such variable for each local variable. We also show experimental results on bounded model checking for our algorithm compared with the previous work by Long and Seawright.
• 書誌レコードID / 収録物識別子タイプ: NCID
• 書誌レコードID / 収録物識別子: AA12394951
• 書誌情報: IPSJ Transactions on System LSI Design Methodology （TSLDM）; 巻 2, p. 80-92, 発行日 2009-02-17
• ISSN / 収録物識別子タイプ: ISSN
• ISSN / 収録物識別子: 1882-6687
• 出版者 / 言語: ja
• 出版者: 情報処理学会