A Behavioral Synthesis System for Asynchronous Circuits with Bundled-data Implementation

• Item type: Trans(1)
• 公開日: 2009-02-17
• タイトル: A Behavioral Synthesis System for Asynchronous Circuits with Bundled-data Implementation
• タイトル / 言語: en
• タイトル: A Behavioral Synthesis System for Asynchronous Circuits with Bundled-data Implementation
• 言語: eng
• キーワード / 主題Scheme: Other
• キーワード / 主題: Asynchronous Behavioral Synthesis
• 資源タイプ / 資源タイプ識別子: http://purl.org/coar/resource_type/c_6501
• 資源タイプ: journal article
• 著者所属: The University of Aizu, Japan
• 著者所属: The University of Aizu, Japan
• 著者所属: The University of Aizu, Japan
• 著者所属: The University of Aizu, Japan
• 著者所属: National Institute of Informatics, Japan
• 著者所属: The University of Utah, USA
• 著者所属: The University of Tokyo, Japan
• 著者所属(英): en
• 著者所属(英): The University of Aizu, Japan
• 著者所属(英): en
• 著者所属(英): The University of Aizu, Japan
• 著者所属(英): en
• 著者所属(英): The University of Aizu, Japan
• 著者所属(英): en
• 著者所属(英): The University of Aizu, Japan
• 著者所属(英): en
• 著者所属(英): National Institute of Informatics, Japan
• 著者所属(英): en
• 著者所属(英): The University of Utah, USA
• 著者所属(英): en
• 著者所属(英): The University of Tokyo, Japan
• 著者名: Naohiro, Hamada; Yuki, Shiga; Takao, Konishi; Hiroshi, Saito; Tomohiro, Yoneda; Chris, Myers; Takashi, Nanya
• 著者名(英): Naohiro, Hamada; Yuki, Shiga; Takao, Konishi; Hiroshi, Saito; Tomohiro, Yoneda; Chris, Myers; Takashi, Nanya
• 論文抄録 / 内容記述タイプ: Other
• 論文抄録 / 内容記述: This paper proposes a behavioral synthesis system for asynchronous circuits with bundled-data implementation. The proposed system is based on a behavioral synthesis method for synchronous circuits and extended on operation scheduling and control synthesis for bundled-data implementation. The proposed system synthesizes an RTL model and a simulation model from a behavioral description specified by a restricted C language, a resource library, and a set of design constraints. This paper shows the effectiveness of the proposed system in terms of area and latency through comparisons among bundled-data implementations synthesized by the proposed system, synchronous counterparts, and bundled-data implementations synthesized by using a behavioral synthesis method for synchronous circuits directly.
• 論文抄録(英) / 内容記述タイプ: Other
• 論文抄録(英) / 内容記述: This paper proposes a behavioral synthesis system for asynchronous circuits with bundled-data implementation. The proposed system is based on a behavioral synthesis method for synchronous circuits and extended on operation scheduling and control synthesis for bundled-data implementation. The proposed system synthesizes an RTL model and a simulation model from a behavioral description specified by a restricted C language, a resource library, and a set of design constraints. This paper shows the effectiveness of the proposed system in terms of area and latency through comparisons among bundled-data implementations synthesized by the proposed system, synchronous counterparts, and bundled-data implementations synthesized by using a behavioral synthesis method for synchronous circuits directly.
• 書誌レコードID / 収録物識別子タイプ: NCID
• 書誌レコードID / 収録物識別子: AA12394951
• 書誌情報: IPSJ Transactions on System LSI Design Methodology （TSLDM）; 巻 2, p. 64-79, 発行日 2009-02-17
• ISSN / 収録物識別子タイプ: ISSN
• ISSN / 収録物識別子: 1882-6687
• 出版者 / 言語: ja
• 出版者: 情報処理学会