Hardware Verification at Functional Design Stage

• Item type: JInfP(1)
• 公開日: 1980-09-30
• タイトル: Hardware Verification at Functional Design Stage
• タイトル / 言語: en
• タイトル: Hardware Verification at Functional Design Stage
• 言語: eng
• 資源タイプ / 資源タイプ識別子: http://purl.org/coar/resource_type/c_6501
• 資源タイプ: journal article
• 著者所属: Information Processing Laboratory Fujitsu Laboratories Ltd.
• 著者所属(英): en
• 著者所属(英): Information Processing Laboratory, Fujitsu Laboratories Ltd.
• 著者名: Fumihiro, Maruyama
• 著者名(英): Fumihiro, Maruyama
• 論文抄録 / 内容記述タイプ: Other
• 論文抄録 / 内容記述: With the increasing use of LSIs in computers them has been a greater demand for high reliability in logic design. In order to respond to this demand we have introduced formal design description into the functional design stage by means of the hardware description language DDL and have developed a simulator and a translator which extracts and arranges the information for circuit design from the DDL functional descriptions. Here the research findings on the verification of logic design are reported. Although there are several publications on research results in this field they deal only with applications of the proof of theorems or the testing method for programs. In this paper a new method of verification is presented that fully exploits the state transition representation used conventionally in hardware design. The method described here detects the inconsistencies in the hardware functional d6criptions and verifies that the hardware meets the given specifications using the information extracted and arranged by the translator from the DDL functional descriptions in the state transition representation. This method is aimed basically at verifying the logic design of large-scale computers and provides an effective veriticatiorl algorithm for checking the interfaces between units in which problems of erroneous design are more frequent. Although this method is currently being evaluated using a conversational-mode test system it is considered to be extremely effective for detecting design errors that cannot be detected by ordinary simulations and for finding the causes of conditions that the designer never expected.
• 論文抄録(英) / 内容記述タイプ: Other
• 論文抄録(英) / 内容記述: With the increasing use of LSIs in computers, them has been a greater demand for high reliability in logic design. In order to respond to this demand, we have introduced formal design description into the functional design stage by means of the hardware description language DDL, and have developed a simulator and a translator, which extracts and arranges the information for circuit design from the DDL functional descriptions. Here the research findings on the verification of logic design are reported. Although there are several publications on research results in this field, they deal only with applications of the proof of theorems or the testing method for programs. In this paper, a new method of verification is presented that fully exploits the state transition representation used conventionally in hardware design. The method described here detects the inconsistencies in the hardware functional d6criptions and verifies that the hardware meets the given specifications, using the information extracted and arranged by the translator from the DDL functional descriptions in the state transition representation. This method is aimed basically at verifying the logic design of large-scale computers and provides an effective veriticatiorl algorithm for checking the interfaces between units, in which problems of erroneous design are more frequent. Although this method is currently being evaluated using a conversational-mode test system, it is considered to be extremely effective for detecting design errors that cannot be detected by ordinary simulations, and for finding the causes of conditions that the designer never expected.
• 書誌レコードID / 収録物識別子タイプ: NCID
• 書誌レコードID / 収録物識別子: AA00700121
• 書誌情報: Journal of Information Processing; 巻 3, 号 3, p. 152-161, 発行日 1980-09-30
• ISSN / 収録物識別子タイプ: ISSN
• ISSN / 収録物識別子: 1882-6652
• 出版者 / 言語: ja
• 出版者: 情報処理学会