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A 64-bit RISC Microprocessor for Parallel Computer Systems
https://ipsj.ixsq.nii.ac.jp/records/59749
https://ipsj.ixsq.nii.ac.jp/records/597497055fb7b-6c56-47b1-88ec-f19dbd19c846
| 名前 / ファイル | ライセンス | アクション |
|---|---|---|
IPSJ-JIP1302006.pdf (812.8 kB)
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Copyright (c) 1990 by the Information Processing Society of Japan
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| オープンアクセス | ||
| Item type | JInfP(1) | |||||||
|---|---|---|---|---|---|---|---|---|
| 公開日 | 1990-08-25 | |||||||
| タイトル | ||||||||
| タイトル | A 64-bit RISC Microprocessor for Parallel Computer Systems | |||||||
| タイトル | ||||||||
| 言語 | en | |||||||
| タイトル | A 64-bit RISC Microprocessor for Parallel Computer Systems | |||||||
| 言語 | ||||||||
| 言語 | eng | |||||||
| 資源タイプ | ||||||||
| 資源タイプ識別子 | http://purl.org/coar/resource_type/c_6501 | |||||||
| 資源タイプ | journal article | |||||||
| 著者所属 | ||||||||
| Information and Communications Research Center Matsushita Electric Industrial Co. Ltd. | ||||||||
| 著者所属 | ||||||||
| Semiconductor Research Center Matsushita EIectric Industrial Co. Ltd. | ||||||||
| 著者所属 | ||||||||
| Semiconductor Research Center Matsushita EIectric Industrial Co. Ltd. | ||||||||
| 著者所属 | ||||||||
| Semiconductor Research | ||||||||
| 著者所属(英) | ||||||||
| en | ||||||||
| Information and Communications Research Center, Matsushita Electric Industrial Co. Ltd. | ||||||||
| 著者所属(英) | ||||||||
| en | ||||||||
| Semiconductor Research Center, Matsushita EIectric Industrial Co. Ltd. | ||||||||
| 著者所属(英) | ||||||||
| en | ||||||||
| Semiconductor Research Center, Matsushita EIectric Industrial Co. Ltd. | ||||||||
| 著者所属(英) | ||||||||
| en | ||||||||
| Semiconductor Research | ||||||||
| 著者名 |
Yuji, Tanikawa
× Yuji, Tanikawa
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| 著者名(英) |
Yuji, Tanikawa
× Yuji, Tanikawa
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| 論文抄録 | ||||||||
| 内容記述タイプ | Other | |||||||
| 内容記述 | This paper describes a microprocessor designed for a (Processing Element) PE of a scientific parallel computer system. This processor consists of three operational units: an instruction fetch and decode unit an integer/address operation unit and a floating-point operation unit. The chip is fabricated by means of a two-AI-layer 1.2 /ヵk N-well CMOS technology and contains 440 K transistors in a 14.4 x 13.5 mm^2 die. The processor which employs RlSC architecture and Harvard-style bus organization executes most of its 47 instructions including 64-bit floating-point operations in one 50-nsec cycle (20 MFLOPS/20 MIPS) with a 5-stage pipeline organization. The performance of the processor and its special functions for parallel computer systems are also discussed. | |||||||
| 論文抄録(英) | ||||||||
| 内容記述タイプ | Other | |||||||
| 内容記述 | This paper describes a microprocessor designed for a (Processing Element) PE of a scientific parallel computer system. This processor consists of three operational units: an instruction fetch and decode unit, an integer/address operation unit, and a floating-point operation unit. The chip is fabricated by means of a two-AI-layer, 1.2 /ヵk N-well CMOS technology, and contains 440 K transistors in a 14.4 x 13.5 mm^2 die. The processor, which employs RlSC architecture and Harvard-style bus organization, executes most of its 47 instructions, including 64-bit floating-point operations, in one 50-nsec cycle (20 MFLOPS/20 MIPS) with a 5-stage pipeline organization. The performance of the processor and its special functions for parallel computer systems are also discussed. | |||||||
| 書誌レコードID | ||||||||
| 収録物識別子タイプ | NCID | |||||||
| 収録物識別子 | AA00700121 | |||||||
| 書誌情報 |
Journal of Information Processing 巻 13, 号 2, p. 150-155, 発行日 1990-08-25 |
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| ISSN | ||||||||
| 収録物識別子タイプ | ISSN | |||||||
| 収録物識別子 | 1882-6652 | |||||||
| 出版者 | ||||||||
| 言語 | ja | |||||||
| 出版者 | 情報処理学会 | |||||||
