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Completeness of Logical Functions Realized by Asynchronous Sequential Circuits
https://ipsj.ixsq.nii.ac.jp/records/59704
https://ipsj.ixsq.nii.ac.jp/records/5970403543497-0db7-4f14-928a-71ee57d55ec0
| 名前 / ファイル | ライセンス | アクション |
|---|---|---|
IPSJ-JIP1402006.pdf (761.0 kB)
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Copyright (c) 1991 by the Information Processing Society of Japan
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| オープンアクセス | ||
| Item type | JInfP(1) | |||||||
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| 公開日 | 1991-07-31 | |||||||
| タイトル | ||||||||
| タイトル | Completeness of Logical Functions Realized by Asynchronous Sequential Circuits | |||||||
| タイトル | ||||||||
| 言語 | en | |||||||
| タイトル | Completeness of Logical Functions Realized by Asynchronous Sequential Circuits | |||||||
| 言語 | ||||||||
| 言語 | eng | |||||||
| 資源タイプ | ||||||||
| 資源タイプ識別子 | http://purl.org/coar/resource_type/c_6501 | |||||||
| 資源タイプ | journal article | |||||||
| 著者所属 | ||||||||
| Department of Information and Computer Sciences Faculty of Engineering Saitama University. | ||||||||
| 著者所属 | ||||||||
| Divison of Natural Science International Christian University. | ||||||||
| 著者所属 | ||||||||
| Yerevan Polytechic Institute. | ||||||||
| 著者所属(英) | ||||||||
| en | ||||||||
| Department of Information and Computer Sciences, Faculty of Engineering, Saitama University. | ||||||||
| 著者所属(英) | ||||||||
| en | ||||||||
| Divison of Natural Science, International Christian University. | ||||||||
| 著者所属(英) | ||||||||
| en | ||||||||
| Yerevan Polytechic Institute. | ||||||||
| 著者名 |
Hisashi, Sato
× Hisashi, Sato
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| 著者名(英) |
Hisashi, Sato
× Hisashi, Sato
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| 論文抄録 | ||||||||
| 内容記述タイプ | Other | |||||||
| 内容記述 | This paper concerns completeness problems for logical functions realized by asynchronous circuits that may have feedback loops. Its first aim is to give mathematical definitions of an asynchronous circuit and of the realization of a logical function by means of an asynchronous circuit. For asynchronous elements the definitions of circuit construction and initialization are very sensitive: a slight modification may have a considerable influence on the completeness. Several types of completeness are then formulated for a set of logical functions (LF- GS- GR- and NS-completeness). The second aim is to give a completeness criterion for each tyupe of completeness. This aim is reatized for LF GS- and GR-completeness. A completeness criterion for NS-completeness is given under a strong condition. | |||||||
| 論文抄録(英) | ||||||||
| 内容記述タイプ | Other | |||||||
| 内容記述 | This paper, concerns completeness problems for logical functions realized by asynchronous circuits that may have feedback loops. Its first aim is to give mathematical definitions of an asynchronous circuit and of the realization of a logical function by means of an asynchronous circuit. For asynchronous elements, the definitions of circuit construction and initialization are very sensitive: a slight modification may have a considerable influence on the completeness. Several types of completeness are then formulated for a set of logical functions (LF-, GS-, GR-, and NS-completeness). The second aim is to give a completeness criterion for each tyupe of completeness. This aim is reatized for LF,GS- and GR-completeness. A completeness criterion for NS-completeness is given under a strong condition. | |||||||
| 書誌レコードID | ||||||||
| 収録物識別子タイプ | NCID | |||||||
| 収録物識別子 | AA00700121 | |||||||
| 書誌情報 |
Journal of Information Processing 巻 14, 号 2, p. 164-171, 発行日 1991-07-31 |
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| ISSN | ||||||||
| 収録物識別子タイプ | ISSN | |||||||
| 収録物識別子 | 1882-6652 | |||||||
| 出版者 | ||||||||
| 言語 | ja | |||||||
| 出版者 | 情報処理学会 | |||||||
