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Design Verification of Sequential Control Circuits Based on Theorem-Proving Method
https://ipsj.ixsq.nii.ac.jp/records/59700
https://ipsj.ixsq.nii.ac.jp/records/59700b018f89f-c222-4ca3-b5c1-fcd3270eea62
| 名前 / ファイル | ライセンス | アクション |
|---|---|---|
IPSJ-JIP1402002.pdf (940.6 kB)
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Copyright (c) 1991 by the Information Processing Society of Japan
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| オープンアクセス | ||
| Item type | JInfP(1) | |||||||
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| 公開日 | 1991-07-31 | |||||||
| タイトル | ||||||||
| タイトル | Design Verification of Sequential Control Circuits Based on Theorem-Proving Method | |||||||
| タイトル | ||||||||
| 言語 | en | |||||||
| タイトル | Design Verification of Sequential Control Circuits Based on Theorem-Proving Method | |||||||
| 言語 | ||||||||
| 言語 | eng | |||||||
| 資源タイプ | ||||||||
| 資源タイプ識別子 | http://purl.org/coar/resource_type/c_6501 | |||||||
| 資源タイプ | journal article | |||||||
| 著者所属 | ||||||||
| Energy Research Laboratory Hitachi Ltd. | ||||||||
| 著者所属 | ||||||||
| Energy Research Laboratory Hitachi Ltd. | ||||||||
| 著者所属 | ||||||||
| Systems Engineering Division Hitachi Ltd. | ||||||||
| 著者所属 | ||||||||
| Computer & Communication Research Center The Tokyo Electric Power Co. | ||||||||
| 著者所属 | ||||||||
| Computer & Communication Research Center The Toky | ||||||||
| 著者所属(英) | ||||||||
| en | ||||||||
| Energy Research Laboratory, Hitachi, Ltd. | ||||||||
| 著者所属(英) | ||||||||
| en | ||||||||
| Energy Research Laboratory, Hitachi, Ltd. | ||||||||
| 著者所属(英) | ||||||||
| en | ||||||||
| Systems Engineering Division, Hitachi, Ltd. | ||||||||
| 著者所属(英) | ||||||||
| en | ||||||||
| Computer & Communication Research Center, The Tokyo Electric Power Co. | ||||||||
| 著者所属(英) | ||||||||
| en | ||||||||
| Computer & Communication Research Center, The Tokyo | ||||||||
| 著者名 |
Naoyuki, Yamada
× Naoyuki, Yamada
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| 著者名(英) |
Naoyuki, Yamada
× Naoyuki, Yamada
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| 論文抄録 | ||||||||
| 内容記述タイプ | Other | |||||||
| 内容記述 | VSEQ (Verifier for SEQential controller) is a design verification system for sequential control circuits in an electric power substation. Instead of using the prevailing simulation techniques it verifies the design by using a theorem-proving method which does not need any test data generation and guarantees reliable verification. Thus VSEQ realizes a theorem-proving method dedicated to the design verification of sequential control circuits. This paper shows that use of domain characteristics in the formulation of the verification problem and also in control of the proof process leads to a theorem-proving method that is efficient enough for practical design verification. | |||||||
| 論文抄録(英) | ||||||||
| 内容記述タイプ | Other | |||||||
| 内容記述 | VSEQ (Verifier for SEQential controller) is a design verification system for sequential control circuits in an electric power substation. Instead of using the prevailing simulation techniques, it verifies the design by using a theorem-proving method, which does not need any test data generation and guarantees reliable verification. Thus VSEQ realizes a theorem-proving method dedicated to the design verification of sequential control circuits. This paper shows that use of domain characteristics in the formulation of the verification problem and also in control of the proof process leads to a theorem-proving method that is efficient enough for practical design verification. | |||||||
| 書誌レコードID | ||||||||
| 収録物識別子タイプ | NCID | |||||||
| 収録物識別子 | AA00700121 | |||||||
| 書誌情報 |
Journal of Information Processing 巻 14, 号 2, p. 126-133, 発行日 1991-07-31 |
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| ISSN | ||||||||
| 収録物識別子タイプ | ISSN | |||||||
| 収録物識別子 | 1882-6652 | |||||||
| 出版者 | ||||||||
| 言語 | ja | |||||||
| 出版者 | 情報処理学会 | |||||||
