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半導体ウェハパターンのための実時間外観検査アルゴリズム
https://ipsj.ixsq.nii.ac.jp/records/53726
https://ipsj.ixsq.nii.ac.jp/records/53726acacdb0d-0664-4bb0-bdd4-39fc7230b501
名前 / ファイル | ライセンス | アクション |
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Copyright (c) 1986 by the Information Processing Society of Japan
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オープンアクセス |
Item type | SIG Technical Reports(1) | |||||||
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公開日 | 1986-03-10 | |||||||
タイトル | ||||||||
タイトル | 半導体ウェハパターンのための実時間外観検査アルゴリズム | |||||||
タイトル | ||||||||
言語 | en | |||||||
タイトル | A real - time image processing algorithm for visual inspection of semiconductor wafer patterns. | |||||||
言語 | ||||||||
言語 | jpn | |||||||
資源タイプ | ||||||||
資源タイプ識別子 | http://purl.org/coar/resource_type/c_18gh | |||||||
資源タイプ | technical report | |||||||
著者所属 | ||||||||
(株)日立製作所中央研究所 | ||||||||
著者所属 | ||||||||
(株)日立製作所中央研究所 | ||||||||
著者所属 | ||||||||
(株)日立製作所中央研究所 | ||||||||
著者所属(英) | ||||||||
en | ||||||||
Central Research Laboratory, Hitachi Ltd. | ||||||||
著者所属(英) | ||||||||
en | ||||||||
Central Research Laboratory, Hitachi Ltd. | ||||||||
著者所属(英) | ||||||||
en | ||||||||
Central Research Laboratory, Hitachi Ltd. | ||||||||
著者名 |
酒匂, 裕
依田, 晴夫
江尻, 正員
× 酒匂, 裕 依田, 晴夫 江尻, 正員
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著者名(英) |
Hiroshi, Sakou
Haruo, Yoda
Masakazu, Ejiri
× Hiroshi, Sakou Haruo, Yoda Masakazu, Ejiri
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論文抄録 | ||||||||
内容記述タイプ | Other | |||||||
内容記述 | The visual inspection of semiconductor wafer patterns requires speedy and accurate extraction of defects and the reliable judgement of their seriousness to the semiconductor function by analysing gray-level wafer image signals. This paper describes an algorithm which can be applied to the real-time image processing. To meet the above requirements the algorithm consists of two parts ; one is for correctly extracting the defects on every region of wafer pattern with the aid of original design data the other is for judging seriousness of the defects by measuring their sizes or the effective pattern widths based on a distance-transform technique. The algorithm is realized as a computer simulation program to confirm its validity. | |||||||
論文抄録(英) | ||||||||
内容記述タイプ | Other | |||||||
内容記述 | The visual inspection of semiconductor wafer patterns requires speedy and accurate extraction of defects and the reliable judgement of their seriousness to the semiconductor function by analysing gray-level wafer image signals. This paper describes an algorithm which can be applied to the real-time image processing. To meet the above requirements, the algorithm consists of two parts ; one is for correctly extracting the defects on every region of wafer pattern with the aid of original design data, the other is for judging seriousness of the defects by measuring their sizes or the effective pattern widths based on a distance-transform technique. The algorithm is realized as a computer simulation program to confirm its validity. | |||||||
書誌レコードID | ||||||||
収録物識別子タイプ | NCID | |||||||
収録物識別子 | AA11131797 | |||||||
書誌情報 |
情報処理学会研究報告コンピュータビジョンとイメージメディア(CVIM) 巻 1986, 号 18(1985-CVIM-041), p. 1-8, 発行日 1986-03-10 |
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Notice | ||||||||
SIG Technical Reports are nonrefereed and hence may later appear in any journals, conferences, symposia, etc. | ||||||||
出版者 | ||||||||
言語 | ja | |||||||
出版者 | 情報処理学会 |