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Performance Evaluation of Instruction Set Architecture of MBP - light : a distributed memory controller for a large scale multiprocessor
https://ipsj.ixsq.nii.ac.jp/records/33365
https://ipsj.ixsq.nii.ac.jp/records/33365144d0087-0d72-450a-8249-e711bb9359a9
| 名前 / ファイル | ライセンス | アクション |
|---|---|---|
IPSJ-MPS03045009.pdf (758.6 kB)
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Copyright (c) 2003 by the Information Processing Society of Japan
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| オープンアクセス | ||
| Item type | SIG Technical Reports(1) | |||||||
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| 公開日 | 2003-06-24 | |||||||
| タイトル | ||||||||
| タイトル | Performance Evaluation of Instruction Set Architecture of MBP - light : a distributed memory controller for a large scale multiprocessor | |||||||
| タイトル | ||||||||
| 言語 | en | |||||||
| タイトル | Performance Evaluation of Instruction Set Architecture of MBP - light : a distributed memory controller for a large scale multiprocessor | |||||||
| 言語 | ||||||||
| 言語 | jpn | |||||||
| 資源タイプ | ||||||||
| 資源タイプ識別子 | http://purl.org/coar/resource_type/c_18gh | |||||||
| 資源タイプ | technical report | |||||||
| 著者所属 | ||||||||
| Department of Computer Science Graduate School of Keio University | ||||||||
| 著者所属 | ||||||||
| Department of Computer Science Graduate School of Keio University | ||||||||
| 著者所属(英) | ||||||||
| en | ||||||||
| Department of Computer Science, Graduate School of Keio University | ||||||||
| 著者所属(英) | ||||||||
| en | ||||||||
| Department of Computer Science, Graduate School of Keio University | ||||||||
| 著者名 |
NORIAKI, SUZUKI
× NORIAKI, SUZUKI
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| 著者名(英) |
Noriaki, Suzuki
× Noriaki, Suzuki
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| 論文抄録 | ||||||||
| 内容記述タイプ | Other | |||||||
| 内容記述 | The instruction set architecture of MBP-light a dedicated for the DSM (Distributed Shared Memory) management of JUMP-1 is analyzed with a real prototype. The Buffer-Register Architecture proposed for MBP-core improves performance with 5.64% in the home cluster and 6.27% in a remote cluster. It appears that the dominant operations in the DSM management program are handling packet queues assigned into the local cluster. Thus common RISC instructions especially load/store instructions are frequently used. Separating instruction and data memory improves performance with 35%. The results suggest that another alternative which provides separate on-chip cache and instructions dedicated for packet queue management is advantageous. | |||||||
| 論文抄録(英) | ||||||||
| 内容記述タイプ | Other | |||||||
| 内容記述 | The instruction set architecture of MBP-light, a dedicated for the DSM (Distributed Shared Memory) management of JUMP-1 is analyzed with a real prototype. The Buffer-Register Architecture proposed for MBP-core improves performance with 5.64% in the home cluster and 6.27% in a remote cluster. It appears that the dominant operations in the DSM management program are handling packet queues assigned into the local cluster. Thus, common RISC instructions, especially load/store instructions, are frequently used. Separating instruction and data memory improves performance with 35%. The results suggest that another alternative which provides separate on-chip cache and instructions dedicated for packet queue management is advantageous. | |||||||
| 書誌レコードID | ||||||||
| 収録物識別子タイプ | NCID | |||||||
| 収録物識別子 | AN10505667 | |||||||
| 書誌情報 |
情報処理学会研究報告数理モデル化と問題解決（MPS） 巻 2003, 号 65(2003-MPS-045), p. 33-36, 発行日 2003-06-24 |
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| Notice | ||||||||
| SIG Technical Reports are nonrefereed and hence may later appear in any journals, conferences, symposia, etc. | ||||||||
| 出版者 | ||||||||
| 言語 | ja | |||||||
| 出版者 | 情報処理学会 | |||||||
