A Reduced Bit - Width Instruction Set Architecture for FQM Execution in Hybrid Processor Architecture（FaRM - rq）

• Item type: SIG Technical Reports(1)
• 公開日: 2003-06-13
• タイトル: A Reduced Bit - Width Instruction Set Architecture for FQM Execution in Hybrid Processor Architecture（FaRM - rq）
• タイトル / 言語: en
• タイトル: A Reduced Bit - Width Instruction Set Architecture for FQM Execution in Hybrid Processor Architecture (FaRM - rq)
• 言語: jpn
• 資源タイプ / 資源タイプ識別子: http://purl.org/coar/resource_type/c_18gh
• 資源タイプ: technical report
• 著者所属: Graduate School of Information Systems The University of Electro - Communications Tokyo Japan
• 著者所属: Graduate School of Information Systems The University of Electro - Communications Tokyo Japan
• 著者所属: Graduate School of Information Systems The University of Electro - Communications Tokyo Japan
• 著者所属: Graduate School of Information Systems The University of Electro - Communications Tokyo Japan
• 著者所属(英): en
• 著者所属(英): Graduate School of Information Systems, The University of Electro - Communications, Tokyo, Japan
• 著者所属(英): en
• 著者所属(英): Graduate School of Information Systems, The University of Electro - Communications, Tokyo, Japan
• 著者所属(英): en
• 著者所属(英): Graduate School of Information Systems, The University of Electro - Communications, Tokyo, Japan
• 著者所属(英): en
• 著者所属(英): Graduate School of Information Systems, The University of Electro - Communications, Tokyo, Japan
• 著者名: BENA.ABDERAZEK; SOICHI, SHIGETA; TSUTOMU, YOSHINAGA; MASAHIRO, SOWA
• 著者名(英): Ben, A.Abderazek; Soichi, Shigeta; Tsutomu, Yoshinaga; Masahiro, Sowa
• 論文抄録 / 内容記述タイプ: Other
• 論文抄録 / 内容記述: Code size is a critical concern in many applications especially for those requiring small code size and special cores. The Queue based instruction set is a promising approach for reducing code size and system complexity. In this paper we present an efficient narrow space instruction set architecture for a Queue mode execution (FQM) in a functional assignment register microprocessor that supports a multi instruction sets through run time functional assignment. In FQM mode the system executes queue based instruction set (termed rwQIS) that are carefully designed with a limited opcode and access to a limited set of special registers. The rwQIS is targeted for a low system complexity and reduced Bit-Width Instructions. In addition to the instruction set architecture we give a measure of the expressive power of FQM instruction set by the relative density and the code ratio of some benchmark programs.
• 論文抄録(英) / 内容記述タイプ: Other
• 論文抄録(英) / 内容記述: Code size is a critical concern in many applications, especially for those requiring small code size and special cores. The Queue based instruction set is a promising approach for reducing code size and system complexity. In this paper, we present an efficient narrow space instruction set architecture for a Queue mode execution (FQM) in a functional assignment register microprocessor that supports a multi instruction sets through run time functional assignment. In FQM mode, the system executes queue based instruction set (termed rwQIS) that are carefully designed with a limited opcode and access to a limited set of special registers. The rwQIS is targeted for a low system complexity and reduced Bit-Width Instructions. In addition to the instruction set architecture, we give a measure of the expressive power of FQM instruction set by the relative density and the code ratio of some benchmark programs.
• 書誌レコードID / 収録物識別子タイプ: NCID
• 書誌レコードID / 収録物識別子: AN10463942
• 書誌情報: 情報処理学会研究報告ハイパフォーマンスコンピューティング（HPC）; 巻 2003, 号 62(2003-HPC-094), p. 19-23, 発行日 2003-06-13
• Notice: SIG Technical Reports are nonrefereed and hence may later appear in any journals, conferences, symposia, etc.
• 出版者 / 言語: ja
• 出版者: 情報処理学会