WEKO3
-
RootNode
アイテム
VLDP Multipath Execution : Mechanism and Evaluation
https://ipsj.ixsq.nii.ac.jp/records/23589
https://ipsj.ixsq.nii.ac.jp/records/235891feafe59-7830-4935-90ed-c7e2c7502d15
| 名前 / ファイル | ライセンス | アクション |
|---|---|---|
IPSJ-ARC01144019.pdf (181.9 kB)
|
Copyright (c) 2001 by the Information Processing Society of Japan
|
|
| オープンアクセス | ||
| Item type | SIG Technical Reports(1) | |||||||
|---|---|---|---|---|---|---|---|---|
| 公開日 | 2001-07-25 | |||||||
| タイトル | ||||||||
| タイトル | VLDP Multipath Execution : Mechanism and Evaluation | |||||||
| タイトル | ||||||||
| 言語 | en | |||||||
| タイトル | VLDP Multipath Execution : Mechanism and Evaluation | |||||||
| 言語 | ||||||||
| 言語 | jpn | |||||||
| 資源タイプ | ||||||||
| 資源タイプ識別子 | http://purl.org/coar/resource_type/c_18gh | |||||||
| 資源タイプ | technical report | |||||||
| 著者所属 | ||||||||
| Graduate School of Engineering The University of Tokyo | ||||||||
| 著者所属 | ||||||||
| Graduate School of Information Science and Technology the University of Tokyo | ||||||||
| 著者所属 | ||||||||
| Graduate School of Engineering The University of Tokyo | ||||||||
| 著者所属 | ||||||||
| Graduate School of Information Science and Technology The University of Tokyo | ||||||||
| 著者所属 | ||||||||
| Graduate School of Information Science and Technology The University of Tokyo | ||||||||
| 著者所属(英) | ||||||||
| en | ||||||||
| Graduate School of Engineering, The University of Tokyo | ||||||||
| 著者所属(英) | ||||||||
| en | ||||||||
| Graduate School of Information Science and Technology, the University of Tokyo | ||||||||
| 著者所属(英) | ||||||||
| en | ||||||||
| Graduate School of Engineering, The University of Tokyo | ||||||||
| 著者所属(英) | ||||||||
| en | ||||||||
| Graduate School of Information Science and Technology, The University of Tokyo | ||||||||
| 著者所属(英) | ||||||||
| en | ||||||||
| Graduate School of Information Science and Technology, The University of Tokyo | ||||||||
| 著者名 |
Shengying, Li
Naoya, Hattori
Yuichiro, Ajima
Shuichi, Sakai
Hidehiko, Tanaka
× Shengying, Li Naoya, Hattori Yuichiro, Ajima Shuichi, Sakai Hidehiko, Tanaka
|
|||||||
| 著者名(英) |
Shengying, Li
Naoya, Hattori
Yuichiro, Ajima
Shuichi, Sakai
Hidehiko, Tanaka
× Shengying, Li Naoya, Hattori Yuichiro, Ajima Shuichi, Sakai Hidehiko, Tanaka
|
|||||||
| 論文抄録 | ||||||||
| 内容記述タイプ | Other | |||||||
| 内容記述 | This paper studies and explores cost-effective execution mechanism for VLDP: a new microprocessor architecture which performs multipath execution on a large number of execution units with distributed registers. Special attention is payed to current development on the interconnection network for distributed register communication. Trace-driven simulations are performed to quantitatively evaluate the execution mechanism. | |||||||
| 論文抄録(英) | ||||||||
| 内容記述タイプ | Other | |||||||
| 内容記述 | This paper studies and explores cost-effective execution mechanism for VLDP: a new microprocessor architecture, which performs multipath execution on a large number of execution units with distributed registers. Special attention is payed to current development on the interconnection network for distributed register communication. Trace-driven simulations are performed to quantitatively evaluate the execution mechanism. | |||||||
| 書誌レコードID | ||||||||
| 収録物識別子タイプ | NCID | |||||||
| 収録物識別子 | AN10096105 | |||||||
| 書誌情報 |
情報処理学会研究報告計算機アーキテクチャ（ARC） 巻 2001, 号 76(2001-ARC-144), p. 105-110, 発行日 2001-07-25 |
|||||||
| Notice | ||||||||
| SIG Technical Reports are nonrefereed and hence may later appear in any journals, conferences, symposia, etc. | ||||||||
| 出版者 | ||||||||
| 言語 | ja | |||||||
| 出版者 | 情報処理学会 | |||||||
