Way - variable Caches for Static Power Reduction

• Item type: SIG Technical Reports(1)
• 公開日: 2003-11-27
• タイトル: Way - variable Caches for Static Power Reduction
• タイトル / 言語: en
• タイトル: Way - variable Caches for Static Power Reduction
• 言語: jpn
• 資源タイプ / 資源タイプ識別子: http://purl.org/coar/resource_type/c_18gh
• 資源タイプ: technical report
• 著者所属: Graduate School of Information Science and Technology The University of Tokyo
• 著者所属: Graduate School of Information Science and Technology The University of Tokyo
• 著者所属: Graduate School of Information Science and Technology The University of Tokyo
• 著者所属: Graduate School of Information Science and Technology The University of Tokyo
• 著者所属: Graduate School of Information Science and Technology The University of Tokyo
• 著者所属(英): en
• 著者所属(英): Graduate School of Information Science and Technology, The University of Tokyo
• 著者所属(英): en
• 著者所属(英): Graduate School of Information Science and Technology, The University of Tokyo
• 著者所属(英): en
• 著者所属(英): Graduate School of Information Science and Technology, The University of Tokyo
• 著者所属(英): en
• 著者所属(英): Graduate School of Information Science and Technology, The University of Tokyo
• 著者所属(英): en
• 著者所属(英): Graduate School of Information Science and Technology, The University of Tokyo
• 著者名: LuongDinhHung; Chitaka, Iwama; NikoDemusBarli; Shuichi, Sakai; Hidehiko, Tanaka
• 著者名(英): Luong, DinhHung; Chitaka, Iwama; Niko, DemusBarli; Shuichi, Sakai; Hidehiko, Tanaka
• 論文抄録 / 内容記述タイプ: Other
• 論文抄録 / 内容記述: Power consumption due to leakage increases rapidly as devices scale to smaller geometries. We propose way-variable caches that dynamically adapt the number of active ways according to runtime requirements. By entirely gating the unused ways from the voltage supply the leakage can be significantly reduced. We then apply an original algorithm utilizing data access locality to make proper resizing decisions. Performance evaluations are done with a superscalar processor model having 16-KB 4-way set-associative L1 instruction and data caches. The results verified that on average 1.7 ways of the instruction cache can be disabled with only 1.3% performance degradation in the case of instruction cache. The values are 1.5 ways and 1.1% in the case of the data cache.
• 論文抄録(英) / 内容記述タイプ: Other
• 論文抄録(英) / 内容記述: Power consumption due to leakage increases rapidly as devices scale to smaller geometries. We propose way-variable caches that dynamically adapt the number of active ways according to runtime requirements. By entirely gating the unused ways from the voltage supply, the leakage can be significantly reduced. We then apply an original algorithm utilizing data access locality to make proper resizing decisions. Performance evaluations are done with a superscalar processor model having 16-KB, 4-way set-associative L1 instruction and data caches. The results verified that, on average, 1.7 ways of the instruction cache can be disabled with only 1.3% performance degradation in the case of instruction cache. The values are 1.5 ways and 1.1% in the case of the data cache.
• 書誌レコードID / 収録物識別子タイプ: NCID
• 書誌レコードID / 収録物識別子: AN10096105
• 書誌情報: 情報処理学会研究報告計算機アーキテクチャ（ARC）; 巻 2003, 号 119(2003-ARC-155), p. 87-92, 発行日 2003-11-27
• Notice: SIG Technical Reports are nonrefereed and hence may later appear in any journals, conferences, symposia, etc.
• 出版者 / 言語: ja
• 出版者: 情報処理学会