The Potential of Temperature-Aware Configurable Cache on Energy Reduction

• Item type: SIG Technical Reports(1)
• 公開日: 2007-05-31
• タイトル: The Potential of Temperature-Aware Configurable Cache on Energy Reduction
• タイトル / 言語: en
• タイトル: The Potential of Temperature-Aware Configurable Cache on Energy Reduction
• 言語: eng
• 資源タイプ / 資源タイプ識別子: http://purl.org/coar/resource_type/c_18gh
• 資源タイプ: technical report
• 著者所属: Department of Informatics Graduate School of Information Science and Electrical Engineering Kyushu University
• 著者所属: System LSI Research Center Kyushu University
• 著者所属: Department of Informatics Graduate School of Information Science and Electrical Engineering Kyushu University
• 著者所属: Department of Informatics Graduate School of Information Science and Electrical Engineering Kyushu University
• 著者所属(英): en
• 著者所属(英): Department of Informatics, Graduate School of Information Science and Electrical Engineering, Kyushu University
• 著者所属(英): en
• 著者所属(英): System LSI Research Center, Kyushu University
• 著者所属(英): en
• 著者所属(英): Department of Informatics, Graduate School of Information Science and Electrical Engineering, Kyushu University
• 著者所属(英): en
• 著者所属(英): Department of Informatics, Graduate School of Information Science and Electrical Engineering, Kyushu University
• 著者名: Hamid, Noori; Maziar, Goudarzi; Koji, INOUE; Kazuaki, MURAKAMI
• 著者名(英): Hamid, Noori; Maziar, Goudarzi; Koji, INOUE; Kazuaki, MURAKAMI
• 論文抄録 / 内容記述タイプ: Other
• 論文抄録 / 内容記述: Active power used to be the primary contributor to total power dissipation of CMOS designs but with the technology scaling the share of leakage in total power consumption of digital systems continues to grow. Moreover temperature is another factor that exponentially increases the leakage current. In this paper we show the effects of temperature and technology nodes on the optimal (minimum-energy-consuming) cache configuration for low energy embedded systems. We show that a temperature-aware configurable cache is an effective way to save energy in finer technologies when the embedded system may be used in different temperatures. Our results show that using a temperature-aware configurable cache up to 66％ energy can be saved with only 1％ performance penalty for instruction cache and 74％ energy saving with 4.7％ performance loss for data cache.
• 論文抄録(英) / 内容記述タイプ: Other
• 論文抄録(英) / 内容記述: Active power used to be the primary contributor to total power dissipation of CMOS designs, but with the technology scaling, the share of leakage in total power consumption of digital systems continues to grow. Moreover, temperature is another factor that exponentially increases the leakage current. In this paper, we show the effects of temperature and technology nodes on the optimal (minimum-energy-consuming) cache configuration for low energy embedded systems. We show that a temperature-aware configurable cache is an effective way to save energy in finer technologies when the embedded system may be used in different temperatures. Our results show that using a temperature-aware configurable cache, up to 66％ energy can be saved with only 1％ performance penalty for instruction cache and 74％ energy saving with 4.7％ performance loss for data cache.
• 書誌レコードID / 収録物識別子タイプ: NCID
• 書誌レコードID / 収録物識別子: AN10096105
• 書誌情報: 情報処理学会研究報告計算機アーキテクチャ（ARC）; 巻 2007, 号 55(2007-ARC-173), p. 13-18, 発行日 2007-05-31
• Notice: SIG Technical Reports are nonrefereed and hence may later appear in any journals, conferences, symposia, etc.
• 出版者 / 言語: ja
• 出版者: 情報処理学会