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Fault-tolerant FPGA Architecture with Distributed Internal Configuration-memory Access
https://ipsj.ixsq.nii.ac.jp/records/22853
https://ipsj.ixsq.nii.ac.jp/records/22853119466d1-5c71-42c6-8704-b09253452c56
| 名前 / ファイル | ライセンス | アクション |
|---|---|---|
IPSJ-ARC08177001.pdf (621.7 kB)
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Copyright (c) 2008 by the Information Processing Society of Japan
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| オープンアクセス | ||
| Item type | SIG Technical Reports(1) | |||||||
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| 公開日 | 2008-03-05 | |||||||
| タイトル | ||||||||
| タイトル | Fault-tolerant FPGA Architecture with Distributed Internal Configuration-memory Access | |||||||
| タイトル | ||||||||
| 言語 | en | |||||||
| タイトル | Fault-tolerant FPGA Architecture with Distributed Internal Configuration-memory Access | |||||||
| 言語 | ||||||||
| 言語 | jpn | |||||||
| 資源タイプ | ||||||||
| 資源タイプ識別子 | http://purl.org/coar/resource_type/c_18gh | |||||||
| 資源タイプ | technical report | |||||||
| 著者所属 | ||||||||
| University of Tokyo | ||||||||
| 著者所属 | ||||||||
| University of Tokyo | ||||||||
| 著者所属 | ||||||||
| University of Tokyo | ||||||||
| 著者所属(英) | ||||||||
| en | ||||||||
| University of Tokyo | ||||||||
| 著者所属(英) | ||||||||
| en | ||||||||
| University of Tokyo | ||||||||
| 著者所属(英) | ||||||||
| en | ||||||||
| University of Tokyo | ||||||||
| 著者名 |
Pierre, Devautour
× Pierre, Devautour
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| 著者名(英) |
Pierre, Devautour
× Pierre, Devautour
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| 論文抄録 | ||||||||
| 内容記述タイプ | Other | |||||||
| 内容記述 | As FPGAs are vulnerable to aging and radiation induced effects that can result in hard errors they need proper autonomous recovery schemes to become really fault-tolerant. But current FPGA architectures have not be designed specifically to support such schemes. This paper presents a fault-tolerant FPGA architecture featuring TMR-based error detection and localization and a distributed internal access to configuration-memory supporting autonomous recovery. | |||||||
| 論文抄録(英) | ||||||||
| 内容記述タイプ | Other | |||||||
| 内容記述 | As FPGAs are vulnerable to aging and radiation induced effects that can result in hard errors, they need proper autonomous recovery schemes to become really fault-tolerant. But current FPGA architectures have not be designed specifically to support such schemes. This paper presents a fault-tolerant FPGA architecture featuring TMR-based error detection and localization and a distributed internal access to configuration-memory supporting autonomous recovery. | |||||||
| 書誌レコードID | ||||||||
| 収録物識別子タイプ | NCID | |||||||
| 収録物識別子 | AN10096105 | |||||||
| 書誌情報 |
情報処理学会研究報告計算機アーキテクチャ（ARC） 巻 2008, 号 19(2008-ARC-177), p. 1-6, 発行日 2008-03-05 |
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| Notice | ||||||||
| SIG Technical Reports are nonrefereed and hence may later appear in any journals, conferences, symposia, etc. | ||||||||
| 出版者 | ||||||||
| 言語 | ja | |||||||
| 出版者 | 情報処理学会 | |||||||
