Cache Controller Design With Run-time Power Gating

• Item type: SIG Technical Reports(1)
• 公開日: 2008-07-29
• タイトル: Cache Controller Design With Run-time Power Gating
• タイトル / 言語: en
• タイトル: Cache Controller Design With Run-time Power Gating
• 言語: eng
• 資源タイプ / 資源タイプ識別子: http://purl.org/coar/resource_type/c_18gh
• 資源タイプ: technical report
• 著者所属: Graduate School of Science and Technology Keio University
• 著者所属: Graduate School of Science and Technology Keio University
• 著者所属: Graduate School of Science and Technology Keio University
• 著者所属: Graduate School of Science and Technology Keio University
• 著者所属: Graduate School of Science and Technology Keio University
• 著者所属: Shibaura Institute of Technolog
• 著者所属: Graduate School of Science and Technology Keio University
• 著者所属(英): en
• 著者所属(英): Graduate School of Science and Technology, Keio University
• 著者所属(英): en
• 著者所属(英): Graduate School of Science and Technology, Keio University
• 著者所属(英): en
• 著者所属(英): Graduate School of Science and Technology, Keio University
• 著者所属(英): en
• 著者所属(英): Graduate School of Science and Technology, Keio University
• 著者所属(英): en
• 著者所属(英): Graduate School of Science and Technology, Keio University
• 著者所属(英): en
• 著者所属(英): Shibaura Institute of Technolog
• 著者所属(英): en
• 著者所属(英): Graduate School of Science and Technology, Keio University
• 著者名: Lei, Zhao; Xu, Hui; Naomi, Seki; Saito, Yoshiki; Yohei, Hasegawa; Kimiyoshi, Usami; Hideharu, Amano
• 著者名(英): Lei, Zhao; Xu, Hui; Naomi, Seki; Saito, Yoshiki; Yohei, Hasegawa; Kimiyoshi, Usami; Hideharu, Amano
• 論文抄録 / 内容記述タイプ: Other
• 論文抄録 / 内容記述: A leakage-efficient cache controller design is presented in this paper. The key insight is that a large circuits subset is accessed only when cache misses happen. By utilizing the run-time power gating technique such a subset can be dynamically powered-off as a power gated domain. Two simple but effective sleeping control polices are proposed to assure the final leakage reduction effect; and to eliminate the impact of wake-up process a latency concellation mechanism is also proposed. Evaluation results show in 90nm CMOS technology 69% and 64% of leakage power can be reduced for instruction cache controller and data cache controller without performance degradation.
• 論文抄録(英) / 内容記述タイプ: Other
• 論文抄録(英) / 内容記述: A leakage-efficient cache controller design is presented in this paper. The key insight is that a large circuits subset is accessed only when cache misses happen. By utilizing the run-time power gating technique, such a subset can be dynamically powered-off as a power gated domain. Two simple but effective sleeping control polices are proposed to assure the final leakage reduction effect; and to eliminate the impact of wake-up process, a latency concellation mechanism is also proposed. Evaluation results show, in 90nm CMOS technology, 69% and 64% of leakage power can be reduced for instruction cache controller and data cache controller without performance degradation.
• 書誌レコードID / 収録物識別子タイプ: NCID
• 書誌レコードID / 収録物識別子: AN10096105
• 書誌情報: 情報処理学会研究報告計算機アーキテクチャ（ARC）; 巻 2008, 号 75(2008-ARC-179), p. 127-132, 発行日 2008-07-29
• Notice: SIG Technical Reports are nonrefereed and hence may later appear in any journals, conferences, symposia, etc.
• 出版者 / 言語: ja
• 出版者: 情報処理学会