Reducing Power of TLB with Power-Gating Technique on Microprocessor

• Item type: SIG Technical Reports(1)
• 公開日: 2008-07-29
• タイトル: Reducing Power of TLB with Power-Gating Technique on Microprocessor
• タイトル / 言語: en
• タイトル: Reducing Power of TLB with Power-Gating Technique on Microprocessor
• 言語: eng
• 資源タイプ / 資源タイプ識別子: http://purl.org/coar/resource_type/c_18gh
• 資源タイプ: technical report
• 著者所属: Graduate School of Science and Technology Keio University
• 著者所属: Graduate School of Science and Technology Keio University
• 著者所属: Department of Computer and Information Sciences Tokyo University of Agriculture and Technology
• 著者所属: Graduate School of Science and Technology Keio University
• 著者所属: Department of Computer and Information Sciences Tokyo University of Agriculture and Technology
• 著者所属: Graduate School of Science and Technology Keio University
• 著者所属(英): en
• 著者所属(英): Graduate School of Science and Technology, Keio University
• 著者所属(英): en
• 著者所属(英): Graduate School of Science and Technology, Keio University
• 著者所属(英): en
• 著者所属(英): Department of Computer and Information Sciences, Tokyo University of Agriculture and Technology
• 著者所属(英): en
• 著者所属(英): Graduate School of Science and Technology, Keio University
• 著者所属(英): en
• 著者所属(英): Department of Computer and Information Sciences, Tokyo University of Agriculture and Technology
• 著者所属(英): en
• 著者所属(英): Graduate School of Science and Technology, Keio University
• 著者名: Xu, hui; Lei, Zhao; Tetsuya, Sunata; Naomi, Seki; Mitaro, Namiki; Hideharu, Amano
• 著者名(英): Xu, hui; Lei, Zhao; Tetsuya, Sunata; Naomi, Seki; Mitaro, Namiki; Hideharu, Amano
• 論文抄録 / 内容記述タイプ: Other
• 論文抄録 / 内容記述: The TLB (translation lookaside buffer) is the hardware that translates the virtual address used by program to the physical address which accesses memory. This high associate structure consumes considerable power of the microprocessor about 16%. The leakage of register file is also a problem while prior work only has looked into reducing dynamic power of TLB. In this paper we use fine-grained RTPG (run-time power gating) technique to reducing TLB leakage power. The main idea is: for iTLB using a recently accessing register to save the sequential accessed entry then power-off the whole iTLB file; for dTLB using counters on every entry when counters exceeds a threshold power-off that entry line. Results with a suite of Mibench mark shows that with the methods for iTLB 67% leakage power can be saved for dTLB 41% leakage power can be saved. Despite the small increase of miss rates the approach can reduce leakage power of TLBs without damaging the performance of microprocessors.
• 論文抄録(英) / 内容記述タイプ: Other
• 論文抄録(英) / 内容記述: The TLB (translation lookaside buffer) is the hardware that translates the virtual address used by program to the physical address, which accesses memory. This high associate structure consumes considerable power of the microprocessor about 16%. The leakage of register file is also a problem, while prior work only has looked into reducing dynamic power of TLB. In this paper, we use fine-grained RTPG (run-time power gating) technique to reducing TLB leakage power. The main idea is: for iTLB, using a recently accessing register to save the sequential accessed entry, then power-off the whole iTLB file; for dTLB using counters on every entry, when counters exceeds a threshold power-off that entry line. Results with a suite of Mibench mark shows that with the methods, for iTLB 67% leakage power can be saved, for dTLB 41% leakage power can be saved. Despite the small increase of miss rates, the approach can reduce leakage power of TLBs, without damaging the performance of microprocessors.
• 書誌レコードID / 収録物識別子タイプ: NCID
• 書誌レコードID / 収録物識別子: AN10096105
• 書誌情報: 情報処理学会研究報告計算機アーキテクチャ（ARC）; 巻 2008, 号 75(2008-ARC-179), p. 121-126, 発行日 2008-07-29
• Notice: SIG Technical Reports are nonrefereed and hence may later appear in any journals, conferences, symposia, etc.
• 出版者 / 言語: ja
• 出版者: 情報処理学会