High-performance Temporal Blocking Stencils at Low GPU Occupancy

• Item type: SIG Technical Reports(1)
• 公開日: 2023-07-27
• タイトル: High-performance Temporal Blocking Stencils at Low GPU Occupancy
• タイトル / 言語: en
• タイトル: High-performance Temporal Blocking Stencils at Low GPU Occupancy
• 言語: eng
• キーワード / 主題Scheme: Other
• キーワード / 主題: 性能最適化
• 資源タイプ / 資源タイプ識別子: http://purl.org/coar/resource_type/c_18gh
• 資源タイプ: technical report
• 著者所属: Tokyo Institute of Technology／National Institute of Advanced Industrial Science and Technology
• 著者所属: RIKEN Center for Computational Science
• 著者所属: National Institute of Advanced Industrial Science and Technology／RIKEN Center for Computational Science
• 著者所属: National Institute of Advanced Industrial Science and Technology
• 著者所属: Tokyo Institute of Technology
• 著者所属: RIKEN Center for Computational Science
• 著者所属(英): en
• 著者所属(英): Tokyo Institute of Technology / National Institute of Advanced Industrial Science and Technology
• 著者所属(英): en
• 著者所属(英): RIKEN Center for Computational Science
• 著者所属(英): en
• 著者所属(英): National Institute of Advanced Industrial Science and Technology / RIKEN Center for Computational Science
• 著者所属(英): en
• 著者所属(英): National Institute of Advanced Industrial Science and Technology
• 著者所属(英): en
• 著者所属(英): Tokyo Institute of Technology
• 著者所属(英): en
• 著者所属(英): RIKEN Center for Computational Science
• 著者名: Lingqi, Zhang; Mohamed, Wahib; Peng, Chen; Yusuke, Tanimura; Toshio, Endo; Satoshi, Matsuoka
• 著者名(英): Lingqi, Zhang; Mohamed, Wahib; Peng, Chen; Yusuke, Tanimura; Toshio, Endo; Satoshi, Matsuoka
• 論文抄録 / 内容記述タイプ: Other
• 論文抄録 / 内容記述: Iterative stencils are used widely across the spectrum of HPC workloads. Many efforts have been put into optimizing stencil GPU kernels, given the prevalence of GPU-accelerated supercomputers. To improve the data locality, temporal blocking is an optimization that combines a batch of time steps to process them together. Under the observation that GPUs are evolving to resemble CPUs in some aspects, we revisit temporal blocking optimizations for GPUs. We explore how temporal blocking schemes can be adapted to the new features in the recent Nvidia GPUs, including large scratchpad memory, hardware prefetching, and device-wide synchronization. We propose a novel temporal blocking method, EBISU, which champions low device occupancy to drive aggressive deep temporal blocking on large tiles that are executed tile-by-tile. Over a wide range of stencil benchmarks, EBISU achieves a geometric mean speedup of 2.0x over any state-of-the-art counterparts.
• 論文抄録(英) / 内容記述タイプ: Other
• 論文抄録(英) / 内容記述: Iterative stencils are used widely across the spectrum of HPC workloads. Many efforts have been put into optimizing stencil GPU kernels, given the prevalence of GPU-accelerated supercomputers. To improve the data locality, temporal blocking is an optimization that combines a batch of time steps to process them together. Under the observation that GPUs are evolving to resemble CPUs in some aspects, we revisit temporal blocking optimizations for GPUs. We explore how temporal blocking schemes can be adapted to the new features in the recent Nvidia GPUs, including large scratchpad memory, hardware prefetching, and device-wide synchronization. We propose a novel temporal blocking method, EBISU, which champions low device occupancy to drive aggressive deep temporal blocking on large tiles that are executed tile-by-tile. Over a wide range of stencil benchmarks, EBISU achieves a geometric mean speedup of 2.0x over any state-of-the-art counterparts.
• 書誌レコードID / 収録物識別子タイプ: NCID
• 書誌レコードID / 収録物識別子: AN10463942
• 書誌情報: 研究報告ハイパフォーマンスコンピューティング（HPC）; 巻 2023-HPC-190, 号 26, p. 1-10, 発行日 2023-07-27
• ISSN / 収録物識別子タイプ: ISSN
• ISSN / 収録物識別子: 2188-8841
• Notice: SIG Technical Reports are nonrefereed and hence may later appear in any journals, conferences, symposia, etc.
• 出版者 / 言語: ja
• 出版者: 情報処理学会