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  3. Asia Pacific Conference on Robot IoT System Development and Platform (APRIS)
  4. 2020

Translation Rules of Regular Expression Code for Hardware Accelerator

https://ipsj.ixsq.nii.ac.jp/records/210325
https://ipsj.ixsq.nii.ac.jp/records/210325
22346a01-8c14-4887-bb26-40b816aab892
名前 / ファイル ライセンス アクション
IPSJ-APRIS2020009.pdf IPSJ-APRIS2020009.pdf (2.0 MB)
Copyright (c) 2021 by the Information Processing Society of Japan
オープンアクセス
Item type Symposium(1)
公開日 2021-03-15
タイトル
タイトル Translation Rules of Regular Expression Code for Hardware Accelerator
タイトル
言語 en
タイトル Translation Rules of Regular Expression Code for Hardware Accelerator
言語
言語 eng
資源タイプ
資源タイプ識別子 http://purl.org/coar/resource_type/c_5794
資源タイプ conference paper
著者所属
Graduate School of Science and Technology, Kumamoto University
著者所属
Faculty of Advanced Science and Technology, Kumamoto University
著者所属
Faculty of Advanced Science and Technology, Kumamoto University
著者所属(英)
en
Graduate School of Science and Technology, Kumamoto University
著者所属(英)
en
Faculty of Advanced Science and Technology, Kumamoto University
著者所属(英)
en
Faculty of Advanced Science and Technology, Kumamoto University
著者名 Hendar, mawan

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Hendar, mawan

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Morihiro, Kuga

× Morihiro, Kuga

Morihiro, Kuga

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Masahiro, Iida

× Masahiro, Iida

Masahiro, Iida

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著者名(英) Hendar, mawan

× Hendar, mawan

en Hendar, mawan

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Morihiro, Kuga

× Morihiro, Kuga

en Morihiro, Kuga

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Masahiro, Iida

× Masahiro, Iida

en Masahiro, Iida

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論文抄録
内容記述タイプ Other
内容記述 In the field of industrial robotics, it is necessary to aggregate sensor information from many edge devices in an IoT environment. Therefore, in situations where real-time is required, it is necessary to perform appropriate load balancing on each tier of edge nodes, intermediate nodes, and server nodes, and to select an adequate embedded processor and to reduce network traffic between nodes. Powerful processors cannot be used on edge nodes that are required to reduce power consumption for low-cost processor. As a solution, heavy duty function of an application is effective to be implemented on FPGA as an accelerator to support the computation to address the power consumption and optimize the performance. Furthermore, real-time data streaming application become ubiquitous in the future, as industrial robotic IoT will required to process all requirement and processing into meaningful information. One of the important streaming data processing is pattern matching algorithm. There is a method to describe search pattern by a regular expression when performing data pattern matching, but it is faster to use an accelerator using hardware FPGA as IoT than using a general-purpose processor. However, it is difficult and time-consuming to design the hardware for the FPGA for each regular expression pattern. In order to improve user convenience, we are researching a method for automatically designing hardware for processing regular expressions by high-level synthesis from C language. In this research, we proposed rules and methods towards translation regular expression pattern into supported hardware code as our contribution to promote HW-SW co-design ecosystem and to allow the efficient utilization of FPGAs with low power consumption and high productivity. The performance evaluation is based on the regular expression algorithm for data streaming application on ARM processor, Core i7 CPU server and FPGA. We challenge the performance of same system of optimized C/C++ and Python Library, RE2C and our proposal rules. While, the proposed rule has been evaluated in lower cost programmable SoC device. Our result shows that it enables to speedup data streaming applications by up to 2000 and 30,000 times of C/C++ Library, 320 and 3400 times of Python Library, 15 and 180 times while compared to RE2C on CPU server and ARM respectively. In the same time reducing significantly the energy consumption with 118,000 [MB/s/J] energy efficiency.
論文抄録(英)
内容記述タイプ Other
内容記述 In the field of industrial robotics, it is necessary to aggregate sensor information from many edge devices in an IoT environment. Therefore, in situations where real-time is required, it is necessary to perform appropriate load balancing on each tier of edge nodes, intermediate nodes, and server nodes, and to select an adequate embedded processor and to reduce network traffic between nodes. Powerful processors cannot be used on edge nodes that are required to reduce power consumption for low-cost processor. As a solution, heavy duty function of an application is effective to be implemented on FPGA as an accelerator to support the computation to address the power consumption and optimize the performance. Furthermore, real-time data streaming application become ubiquitous in the future, as industrial robotic IoT will required to process all requirement and processing into meaningful information. One of the important streaming data processing is pattern matching algorithm. There is a method to describe search pattern by a regular expression when performing data pattern matching, but it is faster to use an accelerator using hardware FPGA as IoT than using a general-purpose processor. However, it is difficult and time-consuming to design the hardware for the FPGA for each regular expression pattern. In order to improve user convenience, we are researching a method for automatically designing hardware for processing regular expressions by high-level synthesis from C language. In this research, we proposed rules and methods towards translation regular expression pattern into supported hardware code as our contribution to promote HW-SW co-design ecosystem and to allow the efficient utilization of FPGAs with low power consumption and high productivity. The performance evaluation is based on the regular expression algorithm for data streaming application on ARM processor, Core i7 CPU server and FPGA. We challenge the performance of same system of optimized C/C++ and Python Library, RE2C and our proposal rules. While, the proposed rule has been evaluated in lower cost programmable SoC device. Our result shows that it enables to speedup data streaming applications by up to 2000 and 30,000 times of C/C++ Library, 320 and 3400 times of Python Library, 15 and 180 times while compared to RE2C on CPU server and ARM respectively. In the same time reducing significantly the energy consumption with 118,000 [MB/s/J] energy efficiency.
書誌情報 Proceedings of Asia Pacific Conference on Robot IoT System Development and Platform

巻 2020, p. 51-58, 発行日 2021-03-15
出版者
言語 ja
出版者 情報処理学会
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Hendar, mawan, Morihiro, Kuga, Masahiro, Iida, 2021: 情報処理学会, 51–58 p.

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