| Item type |
SIG Technical Reports(1) |
| 公開日 |
2020-12-04 |
| タイトル |
|
|
タイトル |
A DNN implementation on FPGAs from the existing DNN framework using HLS |
| タイトル |
|
|
言語 |
en |
|
タイトル |
A DNN implementation on FPGAs from the existing DNN framework using HLS |
| 言語 |
|
|
言語 |
eng |
| キーワード |
|
|
主題Scheme |
Other |
|
主題 |
シミュレーション・高位合成 |
| 資源タイプ |
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|
資源タイプ識別子 |
http://purl.org/coar/resource_type/c_18gh |
|
資源タイプ |
technical report |
| 著者所属 |
|
|
|
Nagoya University |
| 著者所属 |
|
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Nagoya University |
| 著者所属 |
|
|
|
Nanzan University |
| 著者所属 |
|
|
|
Nagoya University |
| 著者所属(英) |
|
|
|
en |
|
|
Nagoya University |
| 著者所属(英) |
|
|
|
en |
|
|
Nagoya University |
| 著者所属(英) |
|
|
|
en |
|
|
Nanzan University |
| 著者所属(英) |
|
|
|
en |
|
|
Nagoya University |
| 著者名 |
Hyunjae, Kim
Ryota, Yamamoto
Shinya, Honda
Masato, Edahiro
|
| 著者名(英) |
Hyunjae, Kim
Ryota, Yamamoto
Shinya, Honda
Masato, Edahiro
|
| 論文抄録 |
|
|
内容記述タイプ |
Other |
|
内容記述 |
DNN (Deep Neural Network) implementation on FPGAs has been actively conducted recently. Although some frameworks can use high speed and memory saving methods such as quantization, only a few frameworks are user friendly. Neural Network Console (NNC) is one of a few frameworks providing a user-friendly experience by GUI. In this paper, we explore implementing the network designed by the NNC on FPGAs. We used various optimization techniques using high-level synthesis, and evaluated execution time. In the case study, we implemented a network where all parameters were quantized to 8 bit integers. By implementing without using any floating-point arithmetic, we confirmed that the accuracy of inferences was comparable to the original network. |
| 論文抄録(英) |
|
|
内容記述タイプ |
Other |
|
内容記述 |
DNN (Deep Neural Network) implementation on FPGAs has been actively conducted recently. Although some frameworks can use high speed and memory saving methods such as quantization, only a few frameworks are user friendly. Neural Network Console (NNC) is one of a few frameworks providing a user-friendly experience by GUI. In this paper, we explore implementing the network designed by the NNC on FPGAs. We used various optimization techniques using high-level synthesis, and evaluated execution time. In the case study, we implemented a network where all parameters were quantized to 8 bit integers. By implementing without using any floating-point arithmetic, we confirmed that the accuracy of inferences was comparable to the original network. |
| 書誌レコードID |
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|
収録物識別子タイプ |
NCID |
|
収録物識別子 |
AA12149313 |
| 書誌情報 |
研究報告組込みシステム（EMB）
巻 2020-EMB-55,
号 4,
p. 1-6,
発行日 2020-12-04
|
| ISSN |
|
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収録物識別子タイプ |
ISSN |
|
収録物識別子 |
2188-868X |
| Notice |
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SIG Technical Reports are nonrefereed and hence may later appear in any journals, conferences, symposia, etc. |
| 出版者 |
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言語 |
ja |
|
出版者 |
情報処理学会 |
IPSJ-EMB20055004.pdf (1.1 MB)
