異種混載メモリを有するシステムにおけるパワーシフティング

• Item type: SIG Technical Reports(1)
• 公開日: 2019-07-17
• タイトル: 異種混載メモリを有するシステムにおけるパワーシフティング
• タイトル / 言語: en
• タイトル: A Case for Power Shifting on Hybrid Memory Based Systems (Unrefereed Workshop Manuscript)
• 言語: eng
• キーワード / 主題Scheme: Other
• キーワード / 主題: メモリとストレージ
• 資源タイプ / 資源タイプ識別子: http://purl.org/coar/resource_type/c_18gh
• 資源タイプ: technical report
• 著者所属: 東京大学
• 著者所属: 東京大学
• 著者所属: Technical University of Munich
• 著者所属: Technical University of Munich
• 著者所属(英): en
• 著者所属(英): The University of Tokyo
• 著者所属(英): en
• 著者所属(英): The University of Tokyo
• 著者所属(英): en
• 著者所属(英): Technical University of Munich
• 著者所属(英): en
• 著者所属(英): Technical University of Munich
• 著者名: 有間, 英志; 塙, 敏博; Carsten, Trinitis; Martin, Schulz
• 著者名(英): Eishi, Arima; Toshihiro, Hanawa; Carsten, Trinitis; Martin, Schulz
• 論文抄録 / 内容記述タイプ: Other
• 論文抄録 / 内容記述: High Performance Computing (HPC) systems are facing severe limitations in both power and memory bandwidth/capacity. By now, these limitations have been addressed individually: to improve performance under a strict power constraint, power shifting, which allocates more power budget on the bottleneck component, is a promising approach; for memory bandwidth/capacity increase, the industry has begun to support hybrid main memory designs that comprise multiple different technologies including emerging memories (e.g., 3D stacked DRAM or NVRAM) in one compute node. However, few works look at the combination of both trends. This work explicitly targets power managements of hybrid memory based HPC systems and make a case for power shifting among components, i.e., CPUs, DRAMs, and NVRAMs. Through our preliminary evaluation, we gained the following insight: the performance bottleneck component changes in accordance with the footprint (or data) size, which then also changes the optimal power budget settings. This result motivates us to develop a software framework toward footprint-aware power shifting.
• 論文抄録(英) / 内容記述タイプ: Other
• 論文抄録(英) / 内容記述: High Performance Computing (HPC) systems are facing severe limitations in both power and memory bandwidth/capacity. By now, these limitations have been addressed individually: to improve performance under a strict power constraint, power shifting, which allocates more power budget on the bottleneck component, is a promising approach; for memory bandwidth/capacity increase, the industry has begun to support hybrid main memory designs that comprise multiple different technologies including emerging memories (e.g., 3D stacked DRAM or NVRAM) in one compute node. However, few works look at the combination of both trends. This work explicitly targets power managements of hybrid memory based HPC systems and make a case for power shifting among components, i.e., CPUs, DRAMs, and NVRAMs. Through our preliminary evaluation, we gained the following insight: the performance bottleneck component changes in accordance with the footprint (or data) size, which then also changes the optimal power budget settings. This result motivates us to develop a software framework toward footprint-aware power shifting.
• 書誌レコードID / 収録物識別子タイプ: NCID
• 書誌レコードID / 収録物識別子: AN10096105
• 書誌情報: 研究報告システム・アーキテクチャ（ARC）; 巻 2019-ARC-237, 号 7, p. 1-6, 発行日 2019-07-17
• ISSN / 収録物識別子タイプ: ISSN
• ISSN / 収録物識別子: 2188-8574
• Notice: SIG Technical Reports are nonrefereed and hence may later appear in any journals, conferences, symposia, etc.
• 出版者 / 言語: ja
• 出版者: 情報処理学会