Stochastic Number Generation with Internal Signals of Peripheral Logic Circuits

• Item type: SIG Technical Reports(1)
• 公開日: 2017-10-30
• タイトル: Stochastic Number Generation with Internal Signals of Peripheral Logic Circuits
• タイトル / 言語: en
• タイトル: Stochastic Number Generation with Internal Signals of Peripheral Logic Circuits
• 言語: eng
• 資源タイプ / 資源タイプ識別子: http://purl.org/coar/resource_type/c_18gh
• 資源タイプ: technical report
• 著者所属: Graduate School of Information Sciences, Hiroshima City University
• 著者所属: Faculty of Information Sciences, Hiroshima City University
• 著者所属: Graduate School of Information Sciences, Hiroshima City University
• 著者所属: Graduate School of Information Sciences, Hiroshima City University
• 著者所属: Graduate School of Information Sciences, Hiroshima City University
• 著者所属(英): en
• 著者所属(英): Graduate School of Information Sciences, Hiroshima City University
• 著者所属(英): en
• 著者所属(英): Faculty of Information Sciences, Hiroshima City University
• 著者所属(英): en
• 著者所属(英): Graduate School of Information Sciences, Hiroshima City University
• 著者所属(英): en
• 著者所属(英): Graduate School of Information Sciences, Hiroshima City University
• 著者所属(英): en
• 著者所属(英): Graduate School of Information Sciences, Hiroshima City University
• 著者名: Naoya, Kubota; Maiki, Fujiha; Hideyuki, Ichihara; Tsuyoshi, Iwagaki; Tomoo, Inoue
• 著者名(英): Naoya, Kubota; Maiki, Fujiha; Hideyuki, Ichihara; Tsuyoshi, Iwagaki; Tomoo, Inoue
• 論文抄録 / 内容記述タイプ: Other
• 論文抄録 / 内容記述: Stochastic computing (SC), which is an approximate computation with probabilities, has attracted attention because it has distinct advantages in hardware cost and fault tolerance. In SC, numbers to be calculated are represented by the probabilities of one occurring in binary sequences and the numbers are transformed from binary (or deterministic) numbers by stochastic number generators (SNGs). In this paper, we propose a new SC scheme in which SNGs of an SC circuit exploit the internal signals of its peripheral logic circuits for generating random numbers. Furthermore, we propose an algorithm for appropriately selecting signal lines so as to reduce both of conversion errors and correlation-induced errors.
• 論文抄録(英) / 内容記述タイプ: Other
• 論文抄録(英) / 内容記述: Stochastic computing (SC), which is an approximate computation with probabilities, has attracted attention because it has distinct advantages in hardware cost and fault tolerance. In SC, numbers to be calculated are represented by the probabilities of one occurring in binary sequences and the numbers are transformed from binary (or deterministic) numbers by stochastic number generators (SNGs). In this paper, we propose a new SC scheme in which SNGs of an SC circuit exploit the internal signals of its peripheral logic circuits for generating random numbers. Furthermore, we propose an algorithm for appropriately selecting signal lines so as to reduce both of conversion errors and correlation-induced errors.
• 書誌レコードID / 収録物識別子タイプ: NCID
• 書誌レコードID / 収録物識別子: AA12149313
• 書誌情報: 研究報告組込みシステム（EMB）; 巻 2017-EMB-46, 号 22, p. 1-6, 発行日 2017-10-30
• ISSN / 収録物識別子タイプ: ISSN
• ISSN / 収録物識別子: 2188-868X
• Notice: SIG Technical Reports are nonrefereed and hence may later appear in any journals, conferences, symposia, etc.
• 出版者 / 言語: ja
• 出版者: 情報処理学会