Multi-stage Pipelining MD5 Implementations on FPGA with Data Forwarding

• Item type: Trans(1)
• 公開日: 2008-12-22
• タイトル: Multi-stage Pipelining MD5 Implementations on FPGA with Data Forwarding
• タイトル / 言語: en
• タイトル: Multi-stage Pipelining MD5 Implementations on FPGA with Data Forwarding
• 言語: eng
• キーワード / 主題Scheme: Other
• キーワード / 主題: 専用システム
• 資源タイプ / 資源タイプ識別子: http://purl.org/coar/resource_type/c_6501
• 資源タイプ: journal article
• 著者所属: Graduate School of Science and Engineering Ritsumeikan University
• 著者所属: Graduate School of Science and Engineering Ritsumeikan University
• 著者所属: Graduate School of Science and Engineering Ritsumeikan University
• 著者所属(英): en
• 著者所属(英): Graduate School of Science and Engineering, Ritsumeikan University
• 著者所属(英): en
• 著者所属(英): Graduate School of Science and Engineering, Ritsumeikan University
• 著者所属(英): en
• 著者所属(英): Graduate School of Science and Engineering, Ritsumeikan University
• 著者名: HoangAnhTuan; Katsuhiro, Yamazaki; Shigeru, Oyanagi
• 著者名(英): Hoang, AnhTuan; Katsuhiro, Yamazaki; Shigeru, Oyanagi
• 論文抄録 / 内容記述タイプ: Other
• 論文抄録 / 内容記述: The MD5 (Message Digest 5) hash algorithm is useful for verifying the correctness and integrity of an arbitrary message but the data dependency in the critical path in its iterations causes a huge computational delay and reduces the system's throughput. This paper describes three-stage and four-stage pipeline MD5 implementations (3SM D5 and 4SM D5) on FPGA which removes the data dependency in the iteration by the data forwarding method and breaks that single step computation into 3 or 4 pipeline stages. The four-stage pipeline with both the keys and the constant table located in the BRAM could operate at the highest frequency because its critical paths are shortened to one adder and some data movements at all stages. The processing of two messages in the alternative form enabled the four-stage pipeline architecture to achieve a higher frequency and throughput than related fine-grained pipelining architectures. Thus the implementations achieve a good trade-off between the hardware size and the throughput.
• 論文抄録(英) / 内容記述タイプ: Other
• 論文抄録(英) / 内容記述: The MD5 (Message Digest 5) hash algorithm is useful for verifying the correctness and integrity of an arbitrary message, but the data dependency in the critical path in its iterations causes a huge computational delay and reduces the system's throughput. This paper describes three-stage and four-stage pipeline MD5 implementations (3SM D5 and 4SM D5) on FPGA, which removes the data dependency in the iteration by the data forwarding method, and breaks that single step computation into 3 or 4 pipeline stages. The four-stage pipeline with both the keys and the constant table located in the BRAM could operate at the highest frequency, because its critical paths are shortened to one adder and some data movements at all stages. The processing of two messages in the alternative form enabled the four-stage pipeline architecture to achieve a higher frequency and throughput than related fine-grained pipelining architectures. Thus, the implementations achieve a good trade-off between the hardware size and the throughput.
• 書誌レコードID / 収録物識別子タイプ: NCID
• 書誌レコードID / 収録物識別子: AA11833852
• 書誌情報: 情報処理学会論文誌コンピューティングシステム（ACS）; 巻 1, 号 3, p. 108-119, 発行日 2008-12-22
• ISSN / 収録物識別子タイプ: ISSN
• ISSN / 収録物識別子: 1882-7829
• 出版者 / 言語: ja
• 出版者: 情報処理学会