RC-002 Reducing Branch Misprediction Penalty in Superscalar Microprocessors by Recovering Critical Misprediction

• Item type: FIT(1)
• 公開日: 2009-08-20
• タイトル / 言語: en
• タイトル: RC-002 Reducing Branch Misprediction Penalty in Superscalar Microprocessors by Recovering Critical Misprediction
• 言語: eng
• 資源タイプ / 資源タイプ識別子: http://purl.org/coar/resource_type/c_5794
• 資源タイプ: conference paper
• 著者所属: 早大
• 著者所属: 早大
• 著者所属: 早大
• 著者所属: 早大
• 著者所属: 早大
• 著者所属(英): en
• 著者所属(英): Graduate School of Information Productions and Systems, Waseda University
• 著者所属(英): en
• 著者所属(英): Graduate School of Information Productions and Systems, Waseda University
• 著者所属(英): en
• 著者所属(英): Graduate School of Information Productions and Systems, Waseda University
• 著者所属(英): en
• 著者所属(英): Graduate School of Information Productions and Systems, Waseda University
• 著者所属(英): en
• 著者所属(英): Graduate School of Information Productions and Systems, Waseda University
• 著者名: 叶, 〓耀; 万, 宇; 董, 宜平; 鮑, 治国; 渡邊, 孝博
• 著者名(英): Ye, Jiongyao; Wan, Yu; Dong, Yiping; Bao, zhiguo; Watanabe, takahiro
• 論文抄録(英) / 内容記述タイプ: Other
• 論文抄録(英) / 内容記述: In modern superscalar processor, branch misprediction penalty becomes a critical factor in overall processor performance, especially in deeply pipelined processors. The branch misprediction penalties include branch resolution time and refill the pipeline. A large number of aggressive schemes (e.g. checkpoint scheme) are widely used in most of current approaches to reduce the branch resolution time. However, current recovery mechanisms still implicitly reduce the Instruction Per Cycle (IPC) because the mispredicted instructions saved in the front-end stages must be flushed, and then the instructions from correct path are restarted from fetch stage. In this paper, we propose a recovery mechanism, called Recovery Critical Misprediction (RCM), to reduce the branch misprediction penalty due to re-fill and flush. The mechanism uses a Simplicity Trace Cache (STC) to trace mispredicted instructions that are enough critical, and selectively forks a second path from STC following a conditional branch instruction. Upon a misprediction, the processor can immediately starts issuing correct instructions from the alternate path. Experimental results employing SPECint 2000 benchmark show that, using a processor with RCM, IPC value is significantly improved by 10.7% on average compared with a conventional processor without RCM.
• 書誌レコードID / 収録物識別子タイプ: NCID
• 書誌レコードID / 収録物識別子: AA1242354X
• 書誌情報: 情報科学技術フォーラム講演論文集; 巻 8, 号 1, p. 121-128, 発行日 2009-08-20
• 出版者 / 言語: ja
• 出版者: 情報処理学会