New Booth Modulo m Multipliers with Signed-Digit Number Arithmetic

• Item type: Journal(1)
• 公開日: 2005-12-15
• タイトル: New Booth Modulo m Multipliers with Signed-Digit Number Arithmetic
• タイトル / 言語: en
• タイトル: New Booth Modulo m Multipliers with Signed-Digit Number Arithmetic
• 言語: eng
• キーワード / 主題Scheme: Other
• キーワード / 主題: 論文
• 資源タイプ / 資源タイプ識別子: http://purl.org/coar/resource_type/c_6501
• 資源タイプ: journal article
• その他タイトル / その他のタイトル: 計算機アーキテクチャ
• 著者所属: Department of Computer Science Gunma University
• 著者所属: Department of Computer Science Gunma University
• 著者所属(英): en
• 著者所属(英): Department of Computer Science Gunma University
• 著者所属(英): en
• 著者所属(英): Department of Computer Science Gunma University
• 著者名: Shuangching, Chen; Shugang, Wei
• 著者名(英): Shuangching, Chen; Shugang, Wei
• 論文抄録 / 内容記述タイプ: Other
• 論文抄録 / 内容記述: New modulo m multipliers with a radix-two signed-digit (SD) number arithmetic is presented by using a modified Booth recoding method. To implement a modulo m multiplication we usually generate modulo m partial products then perform modulo m sum of them. In this paper a new Booth recoding method is proposed to convert a radix-two SD number into a recoded SD (RSD) number in parallel. In the RSD number representation there are no (1 1) and (?1 ?1) at any two-digit position. Thus by using the RSD converted the modulo m partial products can be cut from n into n/2 for an n×n modulo m multiplication. Parallel and serial modulo m multipliers have been designed by using the SD number arithmetic and the proposed Booth recoding. Compared to the former work the area for VLSI implementation of the parallel modulo m multiplier is reduced to 80% from the original design and the speed performance of the serial multiplier is improved up to twice by using the Booth recoding. The implementation method of the proposed Booth modulo m multipliers has been verified by a gate level simulation.
• 論文抄録(英) / 内容記述タイプ: Other
• 論文抄録(英) / 内容記述: New modulo m multipliers with a radix-two signed-digit (SD) number arithmetic is presented by using a modified Booth recoding method. To implement a modulo m multiplication, we usually generate modulo m partial products, then perform modulo m sum of them. In this paper, a new Booth recoding method is proposed to convert a radix-two SD number into a recoded SD (RSD) number in parallel. In the RSD number representation, there are no (1, 1) and (竏驤€1,竏驤€1) at any two-digit position. Thus, by using the RSD converted, the modulo m partial products can be cut from n into n/2 for an n×n modulo m multiplication. Parallel and serial modulo m multipliers have been designed by using the SD number arithmetic and the proposed Booth recoding. Compared to the former work, the area for VLSI implementation of the parallel modulo m multiplier is reduced to 80% from the original design, and the speed performance of the serial multiplier is improved up to twice by using the Booth recoding. The implementation method of the proposed Booth modulo m multipliers has been verified by a gate level simulation.
• 書誌レコードID / 収録物識別子タイプ: NCID
• 書誌レコードID / 収録物識別子: AN00116647
• 書誌情報: 情報処理学会論文誌; 巻 46, 号 12, p. 3030-3039, 発行日 2005-12-15
• ISSN / 収録物識別子タイプ: ISSN
• ISSN / 収録物識別子: 1882-7764