Cache Simulation for Instruction Set Simulator QEMU

• Item type: SIG Technical Reports(1)
• 公開日: 2014-09-10
• タイトル: Cache Simulation for Instruction Set Simulator QEMU
• タイトル / 言語: en
• タイトル: Cache Simulation for Instruction Set Simulator QEMU
• 言語: eng
• キーワード / 主題Scheme: Other
• キーワード / 主題: アーキテクチャ
• 資源タイプ / 資源タイプ識別子: http://purl.org/coar/resource_type/c_18gh
• 資源タイプ: technical report
• 著者所属: Graduate School of Science and Engineering, Ritsumeikan University
• 著者所属: College of Science and Engineering, Ritsumeikan University
• 著者所属: College of Science and Engineering, Ritsumeikan University
• 著者所属(英): en
• 著者所属(英): Graduate School of Science and Engineering, Ritsumeikan University
• 著者所属(英): en
• 著者所属(英): College of Science and Engineering, Ritsumeikan University
• 著者所属(英): en
• 著者所属(英): College of Science and Engineering, Ritsumeikan University
• 著者名: Tran Van, Dung; Ittetsu, Taniguchi; Hiroyuki, Tomiyama
• 著者名(英): Tran Van, Dung; Ittetsu, Taniguchi; Hiroyuki, Tomiyama
• 論文抄録 / 内容記述タイプ: Other
• 論文抄録 / 内容記述: In embedded system design, there is an increasing demand for modeling techniques that can provide both accurate measurements of delay and fast simulation speed. Modeling latency effects of a cache can greatly increase accuracy of the simulation and assist developers to optimize their software. Current solutions have not succeeded in balancing three important factors: speed, accuracy and usability. In this research, we created a cache simulation module inside a well-known instruction set simulator QEMU. Our implementation can simulate various cases of cache configuration and obtain every memory access. In full system simulation, speed is kept at around 73 MIPS on a personal host computer which is close to native execution of ARM Cortex-M3 (125 MIPS at 100 MHz). Compared to the widely used cache simulation tool, Valgrind, our simulator is three time faster.
• 論文抄録(英) / 内容記述タイプ: Other
• 論文抄録(英) / 内容記述: In embedded system design, there is an increasing demand for modeling techniques that can provide both accurate measurements of delay and fast simulation speed. Modeling latency effects of a cache can greatly increase accuracy of the simulation and assist developers to optimize their software. Current solutions have not succeeded in balancing three important factors: speed, accuracy and usability. In this research, we created a cache simulation module inside a well-known instruction set simulator QEMU. Our implementation can simulate various cases of cache configuration and obtain every memory access. In full system simulation, speed is kept at around 73 MIPS on a personal host computer which is close to native execution of ARM Cortex-M3 (125 MIPS at 100 MHz). Compared to the widely used cache simulation tool, Valgrind, our simulator is three time faster.
• 書誌レコードID / 収録物識別子タイプ: NCID
• 書誌レコードID / 収録物識別子: AA12149313
• 書誌情報: 研究報告組込みシステム（EMB）; 巻 2014-EMB-34, 号 4, p. 1-6, 発行日 2014-09-10
• Notice: SIG Technical Reports are nonrefereed and hence may later appear in any journals, conferences, symposia, etc.
• 出版者 / 言語: ja
• 出版者: 情報処理学会