Test and Design-for-Testability Solutions for 3D Integrated Circuits

• Item type: Trans(1)
• 公開日: 2014-08-04
• タイトル: Test and Design-for-Testability Solutions for 3D Integrated Circuits
• タイトル / 言語: en
• タイトル: Test and Design-for-Testability Solutions for 3D Integrated Circuits
• 言語: eng
• キーワード / 主題Scheme: Other
• キーワード / 主題: [Testing] cost modeling, repair, retiming, through-silicon via (TSV), wafer sort
• 資源タイプ / 資源タイプ識別子: http://purl.org/coar/resource_type/c_6501
• 資源タイプ: journal article
• 著者所属: Department of Electrical and Computer Engineering, Duke University
• 著者所属: Department of Electrical and Computer Engineering, Duke University
• 著者所属: Department of Electrical and Computer Engineering, Duke University
• 著者所属: Department of Electrical and Computer Engineering, Duke University
• 著者所属: Department of Electrical and Computer Engineering, Duke University
• 著者所属: Department of Electrical and Computer Engineering, Duke University
• 著者所属(英): en
• 著者所属(英): Department of Electrical and Computer Engineering, Duke University
• 著者所属(英): en
• 著者所属(英): Department of Electrical and Computer Engineering, Duke University
• 著者所属(英): en
• 著者所属(英): Department of Electrical and Computer Engineering, Duke University
• 著者所属(英): en
• 著者所属(英): Department of Electrical and Computer Engineering, Duke University
• 著者所属(英): en
• 著者所属(英): Department of Electrical and Computer Engineering, Duke University
• 著者所属(英): en
• 著者所属(英): Department of Electrical and Computer Engineering, Duke University
• 著者名: Krishnendu, Chakrabarty; Mukesh, Agrawal; Sergej, Deutsch; Brandon, Noia; Ran, Wang; Fangming, Ye
• 著者名(英): Krishnendu, Chakrabarty; Mukesh, Agrawal; Sergej, Deutsch; Brandon, Noia; Ran, Wang; Fangming, Ye
• 論文抄録 / 内容記述タイプ: Other
• 論文抄録 / 内容記述: Despite the promise and benefits offered by 3D integration, testing remains a major obstacle that hinders its widespread adoption. Test techniques and design-for-testability (DfT) solutions for 3D ICs are now being studied in the research community, and experts in industry have identified a number of hard problems related to the lack of probe access for wafers, test access in stacked dies, yield enhancement, and new defects arising from unique processing steps. We describe a number of testing and DfT challenges, and present some of the solutions being advocated for these challenges. Techniques highlighted in this paper include: (i) pre-bond testing of TSVs and die logic, including probing and non-invasive test using DfT; (ii) post-bond testing and DfT innovations related to the optimization of die wrappers, test scheduling, and access to dies and inter-die interconnects; (iii) interconnect testing in interposer-based 2.5D ICs; (iv) fault diagnosis and TSV repair; (v) cost modeling and test-flow selection.
• 論文抄録(英) / 内容記述タイプ: Other
• 論文抄録(英) / 内容記述: Despite the promise and benefits offered by 3D integration, testing remains a major obstacle that hinders its widespread adoption. Test techniques and design-for-testability (DfT) solutions for 3D ICs are now being studied in the research community, and experts in industry have identified a number of hard problems related to the lack of probe access for wafers, test access in stacked dies, yield enhancement, and new defects arising from unique processing steps. We describe a number of testing and DfT challenges, and present some of the solutions being advocated for these challenges. Techniques highlighted in this paper include: (i) pre-bond testing of TSVs and die logic, including probing and non-invasive test using DfT; (ii) post-bond testing and DfT innovations related to the optimization of die wrappers, test scheduling, and access to dies and inter-die interconnects; (iii) interconnect testing in interposer-based 2.5D ICs; (iv) fault diagnosis and TSV repair; (v) cost modeling and test-flow selection.
• 書誌レコードID / 収録物識別子タイプ: NCID
• 書誌レコードID / 収録物識別子: AA12394951
• 書誌情報: IPSJ Transactions on System LSI Design Methodology （TSLDM）; 巻 7, p. 56-73, 発行日 2014-08-04
• ISSN / 収録物識別子タイプ: ISSN
• ISSN / 収録物識別子: 1882-6687
• 出版者 / 言語: ja
• 出版者: 情報処理学会