2024-03-19T12:16:56Zhttps://ipsj.ixsq.nii.ac.jp/ej/?action=repository_oaipmhoai:ipsj.ixsq.nii.ac.jp:000112262022-10-21T05:24:51Z00581:00651:00659
Verification and Violation Correction of Timing Constraints for Gate-Level Asynchronous CircuitsVerification and Violation Correction of Timing Constraints for Gate-Level Asynchronous Circuitseng特集:システムLSIの設計技術と設計自動化http://id.nii.ac.jp/1001/00011226/Journal Articlehttps://ipsj.ixsq.nii.ac.jp/ej/?action=repository_action_common_download&item_id=11226&item_no=1&attribute_id=1&file_no=1Copyright (c) 2003 by the Information Processing Society of Japan設計検証Research Center for Advanced Science and Technology The University of TokyoResearch Center for Advanced Science and Technology The University of TokyoResearch Center for Advanced Science and Technology The University of TokyoResearch Center for AMetehan, ÖzcanMasashi, ImaiHiroshi, NakamuraTakashi, NanyaTraditional asynchronous design methodologies basically create correct-by-designcircuits with almost no assumptions on delay values in the circuit. However thisover-pessimism usually creates slow circuits. Recently asynchronous designmethodologies which utilize delay information and apply timing optimizationshave been suggested. These timing optimizations bring new timing constraintsto be observed especially after the layout phase. The aim of this work isto develop a timing verification methodology and an appropriate CAD frameworkfor gate-level asynchronous circuits using well-known static timing analysismethod which will be a bridge between asynchronous logic synthesis toolsand common layout tools. Verification of timing constraints and correction ofviolations (if exist any) after layout are two main objectives. First basic concepts for verification methodology will be given. Then an algorithm for verification and violation correction of timing constraints for general asynchronous circuits is proposed. Later asynchronous data-path circuitsare examined in more detail. Finally current status of the developed CADframework is explained along some experimental results.Traditional asynchronous design methodologies basically create correct-by-designcircuits with almost no assumptions on delay values in the circuit. However, thisover-pessimism usually creates slow circuits. Recently, asynchronous designmethodologies which utilize delay information and apply timing optimizationshave been suggested. These timing optimizations bring new timing constraintsto be observed especially after the layout phase. The aim of this work isto develop a timing verification methodology and an appropriate CAD frameworkfor gate-level asynchronous circuits using well-known static timing analysismethod, which will be a bridge between asynchronous logic synthesis toolsand common layout tools. Verification of timing constraints and correction ofviolations (if exist any) after layout are two main objectives. First, basic concepts for verification methodology will be given. Then, an algorithm for verification and violation correction of timing constraints for general asynchronous circuits is proposed. Later, asynchronous data-path circuitsare examined in more detail. Finally, current status of the developed CADframework is explained along some experimental results.AN00116647情報処理学会論文誌445124412542003-05-151882-77642009-06-29