We developed a message controller (MSC) for a highly parallel processor, CAP-II. The MSC realize interface among a microprocessor (SPARC-IU), cache memories, dynamic RAM modules and I/O devices. It is designed to supply enough data to I/O devices without penalties to calculation. Its design is based on CAP-II architecture, which handles image generations and numerical simulations. A cache controller, which is also incorporated in the MSC, makes it possible to execute a special message transfer (line send). We present the architecture and performance of the MSC.
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