Copyright (c) 2015 by the Institute of Electronics, Information and Communication Engineers This SIG report is only available to those in membership of the SIG.
Faculty of Science and Engineering, Waseda University
Faculty of Science and Engineering, Waseda University
Faculty of Science and Engineering, Waseda University
Faculty of Science and Engineering, Waseda University
Fujitsu Limited
Fujitsu Limited
Faculty of Science and Engineering, Waseda University
Faculty of Science and Engineering, Waseda University
This paper proposes a dynamic scheduling algorithm for multiple automatically parallelized or power reduced applications on a multicore smart devices to gain higher performance and lower power comsumption within the application's deadline. This scheduling algorithm uses the information such as time, power, deadline and number of cores for each application, and is composed of three type of scheduling. Using media codec applications as a benchmark, the proposed scheduling gained 18.5% speedup and 28.8% power reduction compared to FIFO scheduling.
書誌レコードID
AA11451459
雑誌名
研究報告システムとLSIの設計技術（SLDM）
巻
2015-SLDM-170
号
34
ページ
1 - 6
発行年
2015-02-27
Notice
SIG Technical Reports are nonrefereed and hence may later appear in any journals, conferences, symposia, etc.
自動並列化・低消費電力化された複数アプリケーションに対するマルチコア用ダイナミックスケジューリング手法
IPSJ-SLDM15170034.pdf
(1.32MB)
